MEC1322 Datasheet, PDF (95/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 5-21:
Offset
04h
08h
0Ch
10h
14h
18h
20h
24h
28h
2Ch
30h
EC-ONLY REGISTER SUMMARY
Register Name
LPC Bus Monitor Register
Host Bus Error Register
EC SERIRQ Register
EC Clock Control Register
MCHP Test Register
MCHP Test Register
BAR Inhibit Register
MCHP Reserved
MCHP Reserved
MCHP Reserved
LPC BAR Init Register
Note: MCHP Reserved registers are read/write registers. Modifying these registers may have unwanted results.
5.11.1 LPC BUS MONITOR REGISTER
Offset ^04h
Bits
31:2 RESERVED
1 LRESET_STATUS
Description
Type
RES
R
This bit reflects the state of the LRESET# input pin. The LRE-
SET_Status is the inverse of the LRESET# pin.
When the LRESET_Status bit is ‘0b’, the LRESET# input pin is de-
asserted (that is, the pin has the value ‘1b’). When the LRESET_Sta-
tus bit is ‘1b’, the LRESET# input pin is asserted (that is, the pin has
the value ‘0b’).
0 MCHP Reserved
R
5.11.2 HOST BUS ERROR REGISTER
Offset ^08h
Bits
Description
Type
31:8 ErrorAddress[23:16]
This 24-bit field captures the 24-bit internal address of every LPC
transaction whenever the bit LPC_INTERNAL_ERR in this register
is 0. When LPC_INTERNAL_ERR is 1 this register is not updated
but retains its previous value. When bus errors occur this field saves
the address of the first address that caused an error.
5 DMA_ERR
This bit is set to 1 whenever EN_INTERNAL_ERR is 1 and an LPC
DMA access causes an internal bus error. Once set, it remains set
until cleared by being written with a 1.
R
R/WC
Default
-
0h
Reset
Event
-
VCC1_R
ESET
0h
VCC1_R
ESET
Default
0h
Reset
Event
VCC1_R
ESET
0h
VCC1_R
ESET
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DS00001719D-page 95