MEC1322 Datasheet, PDF (310/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
27.8 Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 27-6: EC INTERRUPTS
Source
Description
TXBE_STS
Transmit buffer empty status (TXBE), in the SPI Status Register, sent as
an interrupt request to the Interrupt Aggregator.
RXBF_STS
Receive buffer full status (RXBF), in the SPI Status Register, sent as an
interrupt request to the Interrupt Aggregator.
These status bits are also connected respectively to the DMA Controller’s SPI Controller TX and RX requests signals.
27.9 Low Power Modes
The GP-SPI Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
27.10 Description
The Serial Peripheral Interface (SPI) block is a master SPI block used to communicate with external SPI devices. The
SPI master is responsible for generating the SPI clock and is designed to operate in Full Duplex, Half Duplex, and Dual
modes of operation. The clock source may be programmed to operated at various clock speeds. The data is transmit-
ted serially via 8-bit transmit and receive shift registers. Communication with SPI peripherals that require transactions
of varying lengths can be achieved with multiple 8-bit cycles.
This block has many configuration options: The data may be transmitted and received either MSbit or LSbit first; The
SPI Clock Polarity may be either active high or active low; Data may be sampled or presented on either the rising of
falling edge of the clock (referred to as the transmit clock phase); and the SPI_CLK SPDOUT frequency may be pro-
grammed to a range of values as illustrated in Table 27-7, "SPI_CLK Frequencies". In addition to these many program-
mable options, this feature has several status bits that may be enabled to notify the host that data is being transmitted
or received.
27.10.1 INITIATING AN SPI TRANSACTION
All SPI transactions are initiated by a write to the TX_DATA register. No read or write operations can be initiated until
the Transmit Buffer is Empty, which is indicated by a one in the TXBE status bit.
If the transaction is a write operation, the host writes the TX_DATA register with the value to be transmitted. Writing the
TX_DATA register causes the TXBE status bit to be cleared, indicating that the value has been registered. If empty, the
SPI Core loads this TX_DATA value into an 8-bit transmit shift register and begins shifting the data out. Loading the
value into the shift register causes the TXBE status bit to be asserted, indicating to software that the next byte can be
written to the TX_DATA register.
If the transaction is a read operation, the host initiates a write to the TX_DATA register in the same manner as the write
operation. Unlike the transmit command, the host must clear the RXBF status bit by reading the RX_DATA register
before writing the TX_DATA register. This time, the host will be required to poll the RXBF status bit to determine when
the value in the RX_DATA register is valid.
Note 1: If the SPI interface is configured for Half Duplex mode, the host must still write a dummy byte to receive data.
2: Since RX and TX transactions are executed by the same sequence of transactions, data is always shifted
into the RX_DATA register. Therefore, every write operation causes data to be latched into the RX_DATA
register and the RXBF bit is set. This status bit should be cleared before initiating subsequent transactions.
The host utilizing this SPI core to transmit SPI Data must discard the unwanted receive bytes.
3: The length and order of data sent to and received from a SPI peripheral varies between peripheral devices.
The SPI must be properly configured and software-controlled to communicate with each device and deter-
mine whether SPIRD data is valid slave data.
The following diagrams show sample single byte and multi-byte SPI Transactions.
DS00001719D-page 310
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