MEC1322 Datasheet, PDF (347/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
The PS2_T/R bit must be written to a ‘1’ before initiating another transmission to the remote device. If the PS2_T/R bit
is set to ‘1’ while the channel is actively receiving data (that is, while the status bit RDATA_RDYis ‘1’) prior to the leading
edge of the 10th (parity bit) clock edge, the receive data is discarded. If the bit is set after the 10th edge, the receive
data is saved in the Receive Register.
29.14 Instance Description
29.15 EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the PS/2 Interface. The
addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in the
EC-Only Register Base Address Table.
TABLE 29-8: EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Address Space
PS/2 Interface
0
EC
32-bit internal
address space
1
EC
32-bit internal
address space
2
EC
32-bit internal
address space
3
EC
32-bit internal
address space
Base Address
4000_9000h
4000_9040h
4000_9080h
4000_90C0h
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 29-9: EC-ONLY REGISTER SUMMARY
Offset
Register Name
0h
PS2 Transmit Buffer Register
0h
PS2 Receive Buffer Register
4h
PS2 Control Register
8h
PS2 Status Register
29.15.1 PS2 TRANSMIT BUFFER REGISTER
Offset ^00h
Bits
Description
31:8 Reserved
7:0 TRANSMIT_DATA
Writes to this register start a transmission of the data in this register
to the peripheral.
Type
R
W
Default
-
0h
Reset
Event
-
VCC1_R
ESET
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DS00001719D-page 347