MEC1322 Datasheet, PDF (365/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
32.7 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
32.7.1 POWER DOMAINS
TABLE 32-2: POWER SOURCES
Name
VCC1
32.7.2 CLOCK INPUTS
Description
This power well sources all of the registers and logic in this block.
TABLE 32-3: CLOCK INPUTS
Name
48 MHz Ring Oscillator
32.7.3 RESETS
Description
This clock input is used to derive the TFDP Clk.
TABLE 32-4: RESET SIGNALS
Name
VCC1_RESET
Description
This reset signal resets all of the registers and logic in this block.
32.8 Interrupts
There are no interrupts generated from this block.
32.9 Low Power Modes
The Trace FIFO Debug Port (TFDP) may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR)
circuitry.
32.10 Description
The TFDP is a unidirectional (from processor to external world) two-wire serial, byte-oriented debug interface for use
by processor firmware to transmit diagnostic information.
The TFDP consists of the Debug Data Register, Debug Control Register, a Parallel-to-Serial Converter, a Clock/Control
Interface and a two-pin external interface (TFDP Clk, TFDP Data).
FIGURE 32-2:
BLOCK DIAGRAM OF TFDP DEBUG PORT
Data
Register
PARALLEL-TO-SERIAL
CONVERTER
WRITE_COMPLETE
CLOCK/CONTROL
INTERFACE
TFDP_DAT
TFDP_CLK
 2014 - 2015 Microchip Technology Inc.
DS00001719D-page 365