MEC1322 Datasheet, PDF (275/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
23.0 PECI INTERFACE
23.1 Overview
The MEC1322 includes a PECI Interface to allow the EC to retrieve temperature readings from PECI-compliant
devices. The PECI Interface implements the PHY and Link Layer of a PECI host controller as defined in References[1]
and includes hardware support for the PECI 2.0 command set.
This chapter focuses on MEC1322 specific PECI Interface configuration information such as Power Domains, Clock
Inputs, Resets, Interrupts, and other chip specific information. For a functional description of the MEC1322 PECI Inter-
face refer to References [1].
23.2 References
1. PECI Interface Core, Rev. 1.31, Core-Level Architecture Specification, SMSC Confidential, 4/15/11
23.3 Terminology
No terminology has been defined for this chapter.
23.4 Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
FIGURE 23-1:
PECI INTERFACE I/O DIAGRAM
Host Interface
Power, Clocks and Reset
Interrupts
PECI Interface
PECI_READY
PECI_DAT
23.5 Signal Description
The Signal Description Table lists the signals that are typically routed to the pin interface.
TABLE 23-1: SIGNAL DESCRIPTION TABLE
Name
Direction
Description
PECI_READY
Input
PECI Ready input pin
PECI_DAT
Input/Output
Note: This signal is optional. If this signal is not on the pin inter-
face it is pulled high internally.
PECI Data signal pin
Note: Routing guidelines for the PECI_DAT pin is provided in Intel Platform design guides. Refer to the appropri-
ate Intel document for current information. See Table 23-2.
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DS00001719D-page 275