MEC1322 Datasheet, PDF (276/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 23-2: PECI ROUTING GUIDELINES
Trace Impedance
50 Ohms +/- 15%
Spacing
10 mils
Routing Layer
Microstrip
Trace Width
Calculate to match impedance
Length
1” - 15”
23.6 Host Interface
The registers defined for the PECI Interface are accessible by the various hosts as indicated in Section 23.11, "PECI
Interface Registers".
23.7 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
23.7.1 POWER DOMAINS
TABLE 23-3: POWER SOURCES
Name
VCC1
23.7.2 CLOCK INPUTS
Description
The PECI Interface logic and registers are powered by VCC1.
TABLE 23-4: CLOCK INPUTS
Name
48 MHz Ring Oscillator
23.7.3 RESETS
PECI Module Input Clock
Description
TABLE 23-5: RESET SIGNALS
Name
VCC1_RESET
PECI Core Reset Input
Description
23.8 Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 23-6: EC INTERRUPTS
Source
PECIHOST
PECI Host
Description
23.9 Low Power Modes
The PECI Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
23.10 Instance Description
There is one instance of the PECI Core implemented in the PECI Interface in the MEC1322. See PECI Interface Core,
Rev. 1.31, Core-Level Architecture Specification, SMSC Confidential, 4/15/11 for a description of the PECI Core.
23.11 PECI Interface Registers
The registers listed in the PECI Interface Register Summary table are for a single instance of the PECI Interface. The
addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in the
PECI Interface Register Base Address Table.
DS00001719D-page 276
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