MEC1322 Datasheet, PDF (77/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 5-2: SIGNAL DESCRIPTION TABLE (CONTINUED)
Name
Direction
Description
LFRAME#
LRESET#
Input
Input
Active low signal indicates start of new cycle and termina-
tion of broken cycle.
Active low signal used as LPC Interface Reset. Same as
PCI Reset on host.
LCLK
SERIRQ
CLKRUN#
Input
Input/Output
Open-Drain Output
Note: LRESET# is typically connected to the host
PCI RESET (PCIRST#) signal.
PCI clock input (PCI_CLK)
Serial IRQ pin used with the LCLK signal to transfer inter-
rupts to the host.
Clock Control for LCLK
5.4.2 REGISTER INTERFACES
The registers defined for the LPC Interface block are accessible by the various hosts as indicated in Section 5.9, "LPC
Configuration Registers", Section 5.11, "EC-Only Registers"and Section 5.10, "Runtime Registers".
5.5 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
5.5.1 POWER DOMAINS
TABLE 5-3: POWER SOURCES
Name
Description
VCC1
The LPC Interface block and registers are
powered by VCC1.
5.5.2 CLOCK INPUTS
TABLE 5-4: CLOCK INPUTS
Name
Description
LCLK
This LPC Interface has a single clock input,
called LCLK.
Note:
The PCI_CLK input to LCLK can run at 19.2MHz to 33MHz. When the PCI_CLK input frequency is from
19.2MHz (including 24MHz) to 33MHz the Handshake bit in the EC Clock Control Register must be set to
a ‘1’ to capture LPC transactions properly. See Section 5.11.4, "EC Clock Control Register," on page 96.
5.5.3 RESETS
TABLE 5-5: RESET SIGNALS
Name
VCC1_RESET
nSIO_RESET
LRESET#
Description
Power on Reset to the block. This signal resets all the register and logic
in this block to its default state.
This signal is used to indicate when the main power rail in the system is
reset. The LPC interface is operational when main power is present. This
signal is used to reset selected registers as defined in the Register
Interfaces descriptions.
The LRESET# signal comes from the LPC pin interface. This signal is
defined in the Intel® Low Pin Count (LPC) Interface Specification, v1.1.
The following table defines the effective reset state that result from the combination of these three reset signals.
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DS00001719D-page 77