MEC1322 Datasheet, PDF (160/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
11.17.1 PORT 92 REGISTER
Offset ^0h
Bits
Description
7:2 Reserved
1 ALT_GATE_A20
This bit provides an alternate means for system control of the
GATEA20 pin. ALT_A20 low drives GATEA20 low, if A20 from the
keyboard controller is also low. When Port 92 is enabled, writing a 1
to this bit forces ALT_A20 high. ALT_A20 high drives GATEA20 high
regardless of the state of A20 from the keyboard controller.
0=ALT_A20 is driven low
1=ALT_A20 is driven high
0 ALT_CPU_RESET
This bit provides an alternate means to generate a CPU_RESET
pulse. The CPU_RESET output provides a means to reset the sys-
tem CPU to effect a mode switch from Protected Virtual Address
Mode to the Real Address Mode. This provides a faster means of
reset than is provided through the EC keyboard controller. Writing a
“1” to this bit will cause the ALT_RST# internal signal to pulse (active
low) for a minimum of 6μs after a delay of 14μs. Before another
ALT_RST# pulse can be generated, this bit must be written back to
“0”.
Type
R
R/W
R/W
Default
-
0h
Reset
Event
-
nSIO_R
ESET
0h
nSIO_R
ESET
11.18 Emulated 8042 Interface EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the Legacy Port92/GATEA20
logic. The addresses of each register listed in this table are defined as a relative offset to the host “Base Address”
defined in the EC-Only Register Base Address Table.
TABLE 11-19: EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance Number
Host
Address Space
Base Address
Port92-Legacy
0
EC
32-bit address
400F_1900h
space
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 11-20: EC-ONLY REGISTER SUMMARY
Offset
Register Name (Mnemonic)
0h
GATEA20 Control Register
8h
SETGA20L Register
Ch
RSTGA20L Register
DS00001719D-page 160
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