MEC1322 Datasheet, PDF (153/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
11.13.1 ACTIVATE REGISTER
Offset ^30h
Bits
Description
7:1 Reserved
0 ACTIVATE
1=The 8042 Interface is powered and functional.
0=The 8042 Interface is powered down and inactive.
Type
R
R/W
Default
-
0b
Reset
Event
-
PWRGD
and
VCC1_R
ESET
11.14 Runtime Registers
The registers listed in the Runtime Register Summary table are for a single instance of the Emulated 8042 Interface.
The addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in
the Runtime Register Base Address Table.
Block Instance
Instance Number
Host
Address Space
Base Address
Emulated 8042
0
LPC
I/O
Programmed BAR
Interface
EC
32-bit address
400F_0400h
space
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 11-12: RUNTIME REGISTER SUMMARY
Offset
Register Name (Mnemonic)
00h/04h
00h
04h
HOST_EC Data / CMD Register
EC_HOST Data / AUX Data Register
Keyboard Status Read Register
11.14.1 HOST_EC DATA / CMD REGISTER
Offset ^00h
Bits
Description
7:0 WRITE_DATA
This 8-bit register is write-only. When written, the C/D bit in the Key-
board Status Read Register is cleared to ‘0’, signifying data, and the
IBF in the same register is set to ‘1’.
Type
W
When the Runtime Register at offset 0h is read by the Host, it func-
tions as the EC_HOST Data / AUX Data Register.
Default
0h
Reset
Event
VCC1_R
ESET
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DS00001719D-page 153