MEC1322 Datasheet, PDF (66/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
3.9.13 PCR CHIP SUB-SYSTEM POWER RESET STATUS (CHIP_PWR_RST_STS)
Offset ^34h
Bits
Description
Type
Default
Reset
Event
31:12 RESERVED
11 PCICLK_ACTIVE
This bit monitors the state of the PCI clock input. This status bit
detects edges on the clock input but does not validate the frequency.
0: The 33MHz PCI clock input is not present.
1: The 33MHz PCI clock is present.
10 32K_ACTIVE
This bit monitors the state of the 32K clock input. This status bit
detects edges on the clock input but does not validate the frequency.
0: The 32K clock input is not present. The internal 32K clock is
derived from the ring oscillator
1: The 32K clock input is present. The internal 32K clock is derived
from the pin and the ring oscillator is synchronized to the external
32K clock.
9:7 RESERVED
6 VCC1 reset status
Indicates the status of VCC1_RESET.
0 = No reset occurred since the last time this bit was cleared.
1 = A reset occurred.
RES
R
R
RES
R/WC
-
VCC1_R
ESET
-
VCC1_R
ESET
1h
VCC1_R
ESET
Note:
The bit will not clear if a write 1 is attempted at the same
time that a VCC1_RST_N occurs, this way a reset event
is never missed.
5 VBAT reset status
Indicates the status of VBAT_POR.
0 = No reset occurred while VCC1 was off or since the last time this
bit was cleared.
1 = A reset occurred.
R/WC
-
VCC1_R
ESET
Note:
The bit will not clear if a write 1 is attempted at the same
time that a VBAT_RST_N occurs, this way a reset event
is never missed.
4 RESERVED
RES
3 SIO_Reset Status
Indicates the status of nSIO_RESET.
0 = reset active.
1 = reset not active.
R
xh
Note 3-
15
2 VCC Reset Status
Indicates the status of PWRGD.
0 = reset active (PWRGD not asserted).
1 = reset not active (PWRGD asserted).
R
xh
Note 3-
15
1:0 RESERVED
RES
Note 3-15 This read-only status bit always reflects the current status of the event and is not affected by any
Reset events.
DS00001719D-page 66
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