MEC1322 Datasheet, PDF (97/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Offset ^10h
Bits
1:0 Clock_Control
Description
Type
R/W
This field controls when the host interface will permit the internal ring
oscillator to be shut down. The choices are as follows:
0h: Reserved
1h: The host interface will permit the internal clocks to be shut down
if the CLKRUN# signals “CLOCK STOP” and there are no pending
serial interrupt request or DMA requests from devices associated
with the device. The CLKRUN# signals “CLOCK STOP” by
CLKRUN# being high for 5 LPCCLK’s after the raising edge of
CLKRUN#
2h: The host interface will permit the ring oscillator to be shut down
after the completion of every LPC transaction. This mode may cause
an increase in the time to respond to LPC transactions if the ring
oscillator is off when the LPC transaction is detected.
3h: The ring oscillator is not permitted to shut down as long as the
host interface is active. When the ACTIVATE bit in the LPC Activate
Register is 0, the Host Interface will permit the ring oscillator to be
shut down and the Clock_Control Field is ignored. The Clock_Con-
trol Field only effects the Host Interface when the ACTIVATE bit in
the LPC Activate Register is 1.
5.11.5
Although the Host Interface can permit the internal oscillator to shut
down, it cannot turn the oscillator on in response to an LPC transac-
tion that occurs while the oscillator is off. In order to restart the oscil-
lator in order to complete an LPC transaction, EC firmware must
enable a wake interrupt on the LPC LFRAME# input. See the Appli-
cation Note in Section 15.8.1, "WAKE Generation" for details.
MCHP TEST REGISTER
Offset ^14h
Bits
31:8 RESERVED
7:0 MCHP Reserved
Description
Type
RES
R
5.11.6 MCHP TEST REGISTER
Offset ^18h
Bits
Description
31:2 RESERVED
1 MCHP Reserved
0 MCHP Reserved
Type
RES
R/W
R/W
Default
0h
Reset
Event
VCC1_
RESET
Default
-
0h
Reset
Event
-
VCC1_R
ESET
Default
-
0h
0h
Reset
Event
-
VCC1_R
ESET
VCC1_R
ESET
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DS00001719D-page 97