MEC1322 Datasheet, PDF (408/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
38.10 PS/2 Timing
FIGURE 38-15: PS/2 TRANSMIT TIMING
t2
PS2_CLK
t1
PS2_DAT
PS2_EN
PS2_T/R
XMIT_IDLE
RDATA_RDY
Write Tx Reg
Interrupt
t7
t5
t6
1
2
t8 t9 ^t10
t17
10 11
t4
s
t11
t14
B0
B1 B2 B3 B4
B5 B6 B7
P
t12
t3
t13
t15
Note 1
TABLE 38-14: PS/2 CHANNEL TRANSMISSION TIMING PARAMETERS
Name
Description
MIN
TYP
t1 The PS/2 Channel’s CLK and DATA lines
are floated following PS2_EN=1 and
PS2_T/R=0.
t2 PS2_T/R bit set to CLK driven low prepar-
ing the PS/2 Channel for data transmis-
sion.
t3 CLK line floated to XMIT_IDLE bit de-
asserted.
t4 Trailing edge of WR to Transmit Register to
DATA line driven low.
t5 Trailing edge of EC WR of Transmit Regis-
ter to CLK line floated.
t6 Initiation of Start of Transmit cycle by the
PS/2 channel controller to the auxiliary
peripheral’s responding by latching the
Start bit and driving the CLK line low.
t7 Period of CLK
t8 Duration of CLK high (active)
t9 Duration of CLK low (inactive)
t10
Duration of Data Frame. Falling edge of
Start bit CLK (1st clk) to falling edge of Par-
ity bit CLK (10th clk).
45
90
0.002
60
30
MAX
1000
1.7
90
130
25.003
302
151
2.002
Units
ns
ns
ms
µs
ms
DS00001719D-page 408
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