MEC1322 Datasheet, PDF (172/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
13.9 Low Power Modes
The ACPI PM1 Block Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
13.10 Description
This section describes the functions of the ACPI PM1 Block Interface in more detail.
The MEC1322 implements the ACPI fixed registers but includes only those bits that apply to the power button sleep
button and RTC alarm events. The ACPI WAK_STS, SLP_TYP, and SLP_EN bits are also supported.
The MEC1322 can generate SCI Interrupts to the Host. The functions described in the following sub-sections can gen-
erate a SCI event on the EC_SCI# pin. In the MEC1322, an SCI event is considered the same as an ACPI wakeup or
runtime event.
13.10.1 SCI EVENT-GENERATING FUNCTIONS
Event
Power Button
with Override
Event Bit
PWRBTN_STS
PWRBTNOR_STS
Definition
The power button has a status and an enable bit in the PM1_BLK of regis-
ters to provide an SCI upon the button press. The status bit is software
Read/Writable by the EC; the enable bit is Read-only by the EC. It also has
a status and enable bit in the PM1_BLK of registers to indicate and control
the power button override (fail-safe) event. These bits are not required by
ACPI.
The PWRBTN_STS bit is set by the Host to enable the generation of an
SCI due to the power button event. The status bit is set by the EC when it
generates a power button event and is cleared by the Host writing a ‘1’ to
this bit (writing a ‘0’ has no effect); it can also be cleared by the EC. If the
enable bit is set, the EC generates an SCI power management event.
The power button has a status and an enable bit in the PM1_BLK of regis-
ters to provide an SCI upon the power button override.The power button
override event status bit is software Read/Writable by the EC; the enable bit
is software read-only by the EC.The enable bit for the override event is
located at bit 1 in the Power Management 1 Control Register 2 (PM1_CN-
TRL 2).The power button bit has a status and enable bit in the Runtime
Registers to provide an SCI power management event on a button press
Sleep Button SLPBTN_STS
The PWRBTNOR_STS bit is set by the Host to enable the generation of an
SCI due to the power button override event. The status bit is set by the EC
when it generates a power button event and is cleared by the Host writing a
‘1’ to this bit (writing a ‘0’ has no effect); it can also be cleared by the EC. If
the enable bit is set, the EC generates an SCI power management event.
The sleep button that has a status and an enable bit in the Runtime Regis-
ters to provide an SCI power management event on a button press. The
status bit is software Read/Writable by the EC; the enable bit is Read-only
by the EC.
The SLPBTN_STS bit is set by the Host to enable the generation of an SCI
due to the sleep button event. The status bit is set by the EC when it gener-
ates a sleep button event and is cleared by the Host writing a ‘1’ to this bit
(writing a ‘0’ has no effect); it can also be cleared by the EC. If the enable
bit is set, the EC will generate an SCI power management event.
DS00001719D-page 172
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