MEC1322 Datasheet, PDF (103/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
7.0 ARM M4F BASED EMBEDDED CONTROLLER
7.1 Introduction
This chapter contains a description of the ARM M4F Embedded Controller (EC).
The EC is built around an ARM^® Cortex^®-M4F Processor provided by Arm Ltd. (the “ARM M4F IP”). The ARM Cortex®
M4F is a full-featured 32-bit embedded processor, implementing the ARMv7-M THUMB instruction set and FPU instruc-
tion set in hardware.
The ARM M4F IP is configured as a Von Neumann, Byte-Addressable, Little-Endian architecture. It provides a single
unified 32-bit byte-level address, for a total direct addressing space of 4GByte. It has multiple bus interfaces, but these
express priorities of access to the chip-level resources (Instruction Fetch vs. Data RAM vs. others), and they do not
represent separate addressing spaces.
The ARM M4F IP has configurable options, which are selected as follows.
• Little-Endian byte ordering is selected at all times (hard-wired)
• Bit Banding feature is included for efficient bit-level access.
• Floating-Point Unit (FPU) is included, to implement the Floating-Point instruction set in hardware
• Debug features are included at “Ex+” level, defined as follows:
• DWT Unit provides 4 Data Watchpoint comparators and Execution Monitoring
• FPB Unit provides HW Breakpointing with 6 Instruction and 2 Literal (Read-Only Data) address comparators. The
FPB comparators are also available for Patching: remapping Instruction and Literal Data addresses.
• Trace features are included at “Full” level, defined as follows:
• DWT for reporting breakpoints and watchpoints
• ITM for profiling and to timestamp and output messages from instrumented firmware builds
• ETM for instruction tracing, and for enhanced reporting of Core and DWT events
• The ARM-defined HTM trace feature is not currently included.
• NVIC Interrupt controller with 8 priority levels and up to 240 individually-vectored interrupt inputs.
• A Microchip-defined Interrupt Aggregator function (at chip level) may be used to group multiple interrupts onto sin-
gle NVIC inputs.
• The ARM-defined WIC feature is not currently included.
• Microchip Interrupt Aggregator function (at chip level) is expected to provide Wake control instead.
• The ARM-defined MPU feature is not currently included.
• Memory Protection functionality is not expected to be necessary.
7.2 References
• ARM Limited: Cortex®-M4 Technical Reference Manual, DDI0439C, 29 June 2010
• ARM Limited: ARM®v7-M Architecture Reference Manual, DDI0403D, November 2010
• NOTE: Filename DDI0403D_arm_architecture_v7m_reference_manual_errata_markup_1_0.pdf
• ARM® Generic Interrupt Controller Architecture version 1.0 Architecture Specification, IHI0048A, September 2008
• ARM Limited: AMBA® Specification (Rev 2.0), IHI0011A, 13 May 1999
• ARM Limited: AMBA® 3 AHB-Lite Protocol Specification, IHI0033A, 6 June 2006
• ARM Limited: AMBA® 3 ATB Protocol Specification, IHI0032A, 19 June 2006
• ARM Limited: Cortex-M™ System Design Kit Technical Reference Manual, DDI0479B, 16 June 2011
• ARM Limited: CoreSight™ v1.0 Architecture Specification, IHI0029B, 24 March 2005
• ARM Limited: CoreSight™ Components Technical Reference Manual, DDI0314H, 10 July 2009
• ARM Limited: ARM® Debug Interface v5 Architecture Specification, IHI0031A, 8 February 2006
• ARM Limited: ARM® Debug Interface v5 Architecture Specification ADIv5.1 Supplement, DSA09-PRDC-008772,
17 August 2009
• ARM Limited: Embedded Trace Macrocell™ (ETMv1.0 to ETMv3.5) Architecture Specification, IHI0014Q, 23 Sep-
tember 2011
• ARM Limited: CoreSight™ ETM™-M4 Technical Reference Manual, DDI0440C, 29 June 2010
 2014 - 2015 Microchip Technology Inc.
DS00001719D-page 103