MEC1322 Datasheet, PDF (272/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
22.0 SMBUS INTERFACE
22.1 Introduction
The MEC1322 SMBus Interface includes one instance of the SMBus controller core. This chapter describes aspects of
the SMBus Interface that are unique to the MEC1322 instantiations of this core; including, Power Domain, Resets,
Clocks, Interrupts, Registers and the Physical Interface. For a General Description, Features, Block Diagram, Func-
tional Description, Registers Interface and other core-specific details, see Ref [1] (note: in this chapter, italicized text
typically refers to SMBus controller core interface elements as described in Ref [1]).
22.2 References
1. SMBus Controller Core Interface, Revision 3.4, Core-Level Architecture Specification, SMSC, 7/16/12
22.3 Terminology
There is no terminology defined for this chapter.
22.4 Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface. In
addition, this block is equipped with
FIGURE 22-1:
I/O DIAGRAM OF BLOCK
Host Interface
SMBus Interface
DMA Interface
Power, Clocks and Reset
Interrupts
Signal Description
22.5 Signal Description
The Signal Description Table lists the signals that are typically routed to the pin interface.
TABLE 22-1: SIGNAL DESCRIPTION TABLE
Name
Direction
Description
SMB_DAT0
SMB_CLK0
SMB_DAT1
SMB_CLK1
Input/Output
Input/Output
Input/Output
Input/Output
SMBus Data Port 0
SMBus Clock Port 0
SMBus Data Port 1
SMBus Clock Port 1
Note: The SMB block signals that are shown in Table 22-1 are routed to the SMB pins as listed in Table 22-2.
DS00001719D-page 272
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