MEC1322 Datasheet, PDF (333/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
segments fields in each of the following registers (see Table 28-11): the LED Update Stepsize Register register and the
LED Update Interval Register register. In Asymmetric mode the rising ramp rate uses 4 of the 8 segments fields and the
falling ramp rate uses the remaining 4 of the 8 segments fields (see Table 28-11).
The parameters MIN, MAX, HD, LD and the 8 fields in LED_STEP and LED_INT determine the brightness range of the
LED and the rate at which its brightness changes. See the descriptions of the fields in Section 28.10, "EC-Only Regis-
ters", as well as the examples in Section 28.9.3, "Breathing Examples" for information on how to set these fields.
TABLE 28-11: SYMMETRIC BREATHING MODE REGISTER USAGE
Rising/ Falling
Ramp Times
in Figure 28-3,
"Clipping Example"
Duty Cycle
Segment Index
Symmetric Mode Register Fields Utilized
Note:
X
000xxxxxb
000b
STEP[0]/INT[0]
X
001xxxxxb
001b
STEP[1]/INT[1]
X
010xxxxxb
010b
STEP[2]/INT[2]
X
011xxxxxb
011b
STEP[3]/INT[3]
X
100xxxxxb
100b
STEP[4]/INT[4]
X
101xxxxxb
101b
STEP[5]/INT[5]
X
110xxxxxb
110b
STEP[6]/INT[6]
X
111xxxxxb
111b
STEP[7]/INT[7]
In Symmetric Mode the Segment_Index[2:0] = Duty Cycle Bits[7:5]
Bits[3:0]
Bits[7:4]
Bits[11:8]
Bits[15:12]
Bits[19:16]
Bits[23:20]
Bits[27:24]
Bits[31:28]
TABLE 28-12: ASYMMETRIC BREATHING MODE REGISTER USAGE
Rising/ Falling
Ramp Times
in Figure 28-3,
"Clipping Example"
Duty Cycle
Segment Index Asymmetric Mode Register Fields Utilized
Rising
00xxxxxxb
000b
STEP[0]/INT[0]
Bits[3:0]
Rising
01xxxxxxb
001b
STEP[1]/INT[1]
Bits[7:4]
Rising
10xxxxxxb
010b
STEP[2]/INT[2]
Bits[11:8]
Rising
11xxxxxxb
011b
STEP[3]/INT[3]
Bits[15:12]
falling
00xxxxxxb
100b
STEP[4]/INT[4]
Bits[19:16]
falling
01xxxxxxb
101b
STEP[5]/INT[5]
Bits[23:20]
falling
10xxxxxxb
110b
STEP[6]/INT[6]
Bits[27:24]
falling
11xxxxxxb
111b
STEP[7]/INT[7]
Bits[31:28]
Note: In Asymmetric Mode the Segment_Index[2:0] is the bit concatenation of following: Segment_Index[2] =
(FALLING RAMP TIME in Figure 28-3, "Clipping Example") and Segment_Index[1:0] = Duty Cycle Bits[7:6].
28.9.2 BLINKING CONFIGURATION
The Delay counter and the PWM counter are the same as in the breathing configuration, except in this configuration
they are connected differently. The Delay counter is clocked on either the 32.768 KHz clock or the 48 MHz clock, rather
than the output of the PWM. The PWM counter is clocked by the zero output of the Delay counter, which functions as a
prescalar for the input clocks to the PWM. The Delay counter is reloaded from the LD field of the LED_DELAY register.
When the LD field is 0 the input clock is passed directly to the PWM counter without prescaling. In Blinking/PWM mode
the PWM counter is always 8-bit, and the PSIZE parameter has no effect.
The frequency of the PWM pulse waveform is determined by the formula:
f_PWM = ₍---2---5---6----_×--^f--^c-₍-^l--_L^o---^c_D--^k----+-----1----₎--₎
where f_PWM is the frequency of the PWM, f_clock is the frequency of the input clock (32.768 KHz clock or 48 MHz clock)
and LD is the contents of the LD field.
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DS00001719D-page 333