MEC1322 Datasheet, PDF (304/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
26.9.8 FAN MINIMUM DRIVE REGISTER
the Fan Minimum Drive Register stores the minimum drive setting for the RPM based Fan Control Algorithm. The RPM
based Fan Control Algorithm will not drive the fan at a level lower than the minimum drive unless the target Fan Speed
is set at FFh (see "TACH Target Registers").
During normal operation, if the fan stops for any reason (including low drive), the RPM based Fan Control Algorithm will
attempt to restart the fan. Setting the Fan Minimum Drive Registers to a setting that will maintain fan operation is a useful
way to avoid potential fan oscillations as the control circuitry attempts to drive it at a level that cannot support fan oper-
ation.
These registers only apply if the Fan Speed Control Algorithm is used.
Offset ^08h
Bits
Description
7:0 MIN_DRIVE[7:0]
The minimum drive setting.
Type
R/W
Default
66h
Reset
Event
VCC1_R
ESET
APPLICATION NOTE: To ensure proper operation, the Fan Minimum Drive register must be set prior to setting the
Tach Target High and Low Byte registers, and then the Tach Target registers can be
subsequently updated. At a later time, if the Fan Minimum Drive register is changed to a
value higher than current Fan value, the Tach Target registers must also be updated.
26.9.9 VALID TACH COUNT REGISTER
The Valid TACH Count Register stores the maximum TACH Reading Register value to indicate that the fan is spinning
properly. The value is referenced at the end of the Spin Up Routine to determine if the fan has started operating and
decide if the device needs to retry. See the equation in the TACH Reading Registers section for translating the RPM to
a count.
If the TACH Reading Register value exceeds the Valid TACH Count Register (indicating that the Fan RPM is below the
threshold set by this count), a stalled fan is detected. In this condition, the algorithm will automatically begin its Spin Up
Routine.
APPLICATION NOTE: The automatic invoking of the Spin Up Routine only applies if the Fan Speed Control
Algorithm is used. If the FSC is disabled, then the device will only invoke the Spin Up Routine
when the PWM setting changes from 00h.
If a TACH Target setting is set above the Valid TACH Count setting, that setting will be ignored and the algorithm will
use the current fan drive setting.
These registers only apply if the Fan Speed Control Algorithm is used.
Offset ^09h
Bits
Description
Type
Default
Reset
Event
7:0 VALID_TACH_CNT[7:0]
R/W
The maximum TACH Reading Register value to indicate that the fan
is spinning properly.
F5h
VCC1_R
ESET
26.9.10 FAN DRIVE FAIL BAND REGISTER
The Fan Drive Fail Band Registers store the number of Tach counts used by the Fan Drive Fail detection circuitry. This
circuitry is activated when the fan drive setting high byte is at FFh. When it is enabled, the actual measured fan speed
is compared against the target fan speed.
This circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually capable of reaching.
If the measured fan speed does not exceed the target fan speed minus the Fan Drive Fail Band Register settings for a
period of time longer than set by the DRIVE_FAIL_CNTx[1:0] bits in the Fan Spin Up Configuration Register on page
302, the DRIVE_FAIL status bit will be set and an interrupt generated.
These registers only apply if the Fan Speed Control Algorithm is used.
DS00001719D-page 304
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