MEC1322 Datasheet, PDF (312/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
FIGURE 27-3:
MULTI-BYTE SPI TX/RX TRANSACTIONS (FULL DUPLEX MODE)
MCLK
SPDOUT_Direction
TX_DATA
Write TX_Data
TX_DATA Buffer Empty (TxBE)
Rx_DATA Buffer Full (RxBF)
Read RX_Data
RX_DATA
Data Out Shift Register
Data In Shift Register
SPCLKO
SPI BYTE Transactions
BYTE
0
BYTE 1
BYTE 2
BYTE 0
BYTE 1
BYT
765432107654321076543210
765432107654321076543210
The data may be configured to be transmitted MSB or LSB first. This is configured by the LSBF bit in the SPI Control
Register. The transmit data is shifted out on the edge as selected by the TCLKPH bit in the SPI Clock Control Register.
All received data can be sampled on a rising or falling SPI_CLK edge using the RCLKPH bit in the SPI Clock Control
Register This clock setting must be identical to the clocking requirements of the current SPI slave.
Note: Common peripheral devices require a chip select signal to be asserted during a transaction. Chip selects
for SPI devices may be controlled by MEC1322 GPIO pins.
There are three types of transactions that can be implemented for transmitting and receiving the SPI data. They are Full
Duplex, Half Duplex, and Dual Mode. These modes are define in Section 27.10.3, "Types of SPI Transactions".
27.10.2 DMA MODE
Transmit and receive operations can use a DMA channel. Note that only one DMA channel may be enabled at a
time. Setting up the DMA Controller involves specifying the device (Flash GP-SPI), direction (transmit/receive), and
the start and end addresses of the DMA buffers in the closely couple memory. Please refer to the DMA Controller chap-
ter for register programming information.
SPI transmit / DMA write: the GP-SPI block’s transmit empty (TxBE) status signal is used as a write request to the DMA
controller, which then fetches a byte from the DMA transmit buffer and writes it to the GP-SPI’s SPI TX Data Register
(SPITD). As content of the latter is transferred to the internal Tx shift register from which data is shifted out onto the SPI
bus bit by bit, the Tx Empty signal is again asserted, triggering the DMA fetch-and-write cycle. The process continues
until the end of the DMA buffer is reached - the DMA controller stops responding to an active Tx Empty until the buffer’s
address registers are reprogrammed.
SPI receive / DMA read: the AUTO_READ bit in the SPI Control Register must be set. The driver first writes (dummy
data) to the SPI TX Data Register (SPITD) to initiate the toggling of the SPI clock, enabling data to be shifted in. After
one byte is received, the Rx Full (RxBF) status signal, used as a read request to the DMA controller, is asserted. The
DS00001719D-page 312
 2014 - 2015 Microchip Technology Inc.