MEC1322 Datasheet, PDF (380/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
35.8.3 ETM TRACE ENABLE
Offset ^1Ch
Bits
31:1 Reserved
0 TRACE_EN
Description
Type
R
R/W
35.8.4
This bit enables the ARM TRACE debug port (ETM/ITM). The Trace
Debug Interface pins are forced to the TRACE functions.
0 = ARM TRACE port disabled
1= ARM TRACE port enabled
JTAG ENABLE
Offset ^20h
Bits
31:1 Reserved
0 JTAG_EN
Description
Type
R
R/W
This bit enables the JTAG debug port.
0 = JTAG port disabled. JTAG cannot be enabled (i.e., the TRST#
pin is ignored and the JTAG signals remain in their non-JTAG
state).
1= JTAG port enabled. A high on TRST# enables JTAG
35.8.5 WDT EVENT COUNT
Offset ^28h
Bits
31:4 Reserved
3:0 WDT_COUNT
Description
Type
R
R/W
These EC R/W bits are cleared to 0 on VCC1 POR, but not on a
WDT.
Note:
This field is written by Boot ROM firmware to indicate the
number of times a WDT fired before loading a good EC
code image.
Default
-
0b
Reset
Event
-
VCC1_R
ESET
Default
-
0b
Reset
Event
-
VCC1_R
ESET
Default
-
0b
Reset
Event
-
VCC1_R
ESET
DS00001719D-page 380
 2014 - 2015 Microchip Technology Inc.