MEC1322 Datasheet, PDF (190/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Offset ^05h
Bits
Description
3 FRAME_ERROR
Framing Error. Bit 3 indicates that the received character did not
have a valid stop bit. Bit 3 is set to a logic “1” whenever the stop bit
following the last data bit or parity bit is detected as a zero bit
(Spacing level). This bit is reset to a logic “0” whenever the Line
Status Register is read. In the FIFO mode this error is associated
with the particular character in the FIFO it applies to. This error is
indicated when the associated character is at the top of the FIFO.
The Serial Port will try to resynchronize after a framing error. To do
this, it assumes that the framing error was due to the next start bit,
so it samples this 'start' bit twice and then takes in the 'data'.
2 PARITY ERROR
Parity Error. Bit 2 indicates that the received data character does
not have the correct even or odd parity, as selected by the even
parity select bit. This bit is set to a logic “1” upon detection of a
parity error and is reset to a logic “0” whenever the Line Status
Register is read. In the FIFO mode this error is associated with the
particular character in the FIFO it applies to. This error is indicated
when the associated character is at the top of the FIFO.
1 OVERRUN_ERROR
Overrun Error. Bit 1 indicates that data in the Receiver Buffer Reg-
ister was not read before the next character was transferred into
the register, thereby destroying the previous character. In FIFO
mode, an overrun error will occur only when the FIFO is full and
the next character has been completely received in the shift regis-
ter, the character in the shift register is overwritten but not trans-
ferred to the FIFO. This bit is set to a logic “1” immediately upon
detection of an overrun condition, and reset whenever the Line
Status Register is read.
0 DATA_READY
Data Ready. It is set to a logic ‘1’ whenever a complete incoming
character has been received and transferred into the Receiver
Buffer Register or the FIFO. Bit 0 is reset to a logic ‘0’ by reading
all of the data in the Receive Buffer Register or the FIFO.
Type
R
R
R
R
Default
0h
Reset
Event
RESET
0h
RESET
0h
RESET
0h
RESET
14.11.11 MODEM STATUS REGISTER
Offset ^06h
Bits
Description
7 DCD
This bit is the complement of the Data Carrier Detect (nDCD) input.
If bit 4 of the MCR is set to logic ‘1’, this bit is equivalent to OUT2 in
the MCR.
6 RI#
This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of
the MCR is set to logic ‘1’, this bit is equivalent to OUT1 in the MCR.
Type
R
R
Default
0h
Reset
Event
RESET
0h
RESET
DS00001719D-page 190
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