MEC1322 Datasheet, PDF (273/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 22-2: SIGNAL TO PIN NAME LOOKUP TABLE
Block Name
Pin Name
SMBx_DATn
SMBx_CLKn
I2Cx_DATn
I2Cx_CLKn
Description
SMBus Controller x Port n Data
SMBus Controller x Port n Clock
22.6 Host Interface
The registers defined for the SMBus Interface are accessible as indicated in Section 22.12, "SMBus Registers".
22.7 DMA Interface
This block is designed to communicate with the Internal DMA Controller. This feature is defined in the SMBus Controller
Core Interface specification (See Ref [1]).
Note: For a description of the Internal DMA Controller implemented in this design see Chapter 21.0, "Internal DMA
Controller".
22.8 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
22.8.1 POWER DOMAINS
TABLE 22-3: POWER SOURCES
Name
VCC1
22.8.2 CLOCK INPUTS
Description
This power well sources the registers and logic in this block.
TABLE 22-4: CLOCK INPUTS
Name
48 MHz Ring Oscillator
22.8.3
16MHz_Clk
RESETS
Description
This is the clock signal drives the SMBus controller core. The core also
uses this clock to generate the SMB_CLK on the pin interface.
This is the clock signal is used for baud rate generation.
TABLE 22-5: RESET SIGNALS
Name
VCC1_RESET
Description
This reset signal resets all of the registers and logic in the SMBus
controller core.
22.9 Interrupts
TABLE 22-6:
EC INTERRUPTS
Source
SMB
Description
SMBus Activity Interrupt Event
22.10 Low Power Modes
The SMBus Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
22.11 Description
22.11.1 SMBUS CONTROLLER CORE
The MEC1322 SMBus Interface behavior is defined in the SMBus Controller Core Interface specification (See Ref [1]).
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DS00001719D-page 273