MEC1322 Datasheet, PDF (193/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
15.4.1 SIGNAL INTERFACE
This block is not accessible from the pin interface.
15.4.2 HOST INTERFACE
The registers defined for the EC Interrupt Aggregator are only accessible by the embedded controller via the EC-Only
Registers.
15.5 Power, Clocks and Reset
15.5.1 BLOCK POWER DOMAIN
TABLE 15-1: BLOCK POWER
Power Well Source
Effect on Block
VCC1
The EC Interrupt Aggregator block and registers operate on
this single power well.
15.5.2 BLOCK CLOCKS
None
15.5.3 BLOCK RESET
TABLE 15-2: BLOCK RESETS
Reset Name
Reset Description
VCC1_RESET
This signal is used to indicate when the VCC1 logic and regis-
ters in this block are reset.
15.6 Interrupts
This block aggregates all the interrupts targeted for the embedded controller into the Source Registers defined in Sec-
tion 15.9, "EC-Only Registers," on page 202. The unmasked bits of each source register are then OR’d together and
routed to the embedded controller’s interrupt interface. The name of each Source Register identifies the IRQ number of
the interrupt port on the embedded controller.
15.7 Low Power Modes
This block always automatically adjusts to operate in the lowest power mode.
15.8 Description
The interrupt generation logic is made of 16 groups of signals, each of which consist of a Status register, a Enable reg-
ister and a Result register.
The Status and Enable are latched registers. The Result register is a bit by bit AND function of the Source and Enable
registers. All the bits of the Result register are OR’ed together and AND’ed with the corresponding bit in the Block Select
register to form the interrupt signal that is routed to the ARM interrupt controller.
The Result register bits may also be enabled to the NVIC block via the NVIC_EN bit in the Interrupt Control register.
See Chapter 35.0, "EC Subsystem Registers"
Section 15.8.1 shows a representation of the interrupt structure.
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DS00001719D-page 193