MEC1322 Datasheet, PDF (363/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
31.11.3 BC-LINK DATA REGISTER
Offset ^08h
Bits
Description
Type
31:8 Reserved
R
7:0 DATA
R/W
As described in Section 31.10.1, "BC-Link Master READ Operation"
and Section 31.10.2, "BC-Link Master WRITE Operation", this regis-
ter hold data used in a BC-Link transaction.
31.11.4 BC-LINK CLOCK SELECT REGISTER
Offset ^0Ch
Bits
Description
31:8 Reserved
7:0 DIVIDER
The BC Clock is set to the Master Clock divided by this field, or
48MHz/ (Divider +1). The clock divider bits can only can be changed
when the BC Bus is in soft RESET (when either the Reset bit is set
by software or when the BUSY bit is set by the interface).
Type
R
R/W
Example settings for DIVIDER are shown in Table 31-9, "Example
Frequency Settings".
Default
-
0h
Reset
Event
-
VCC1_R
ESET
Default
-
4h
Reset
Event
-
VCC1_R
ESET
TABLE 31-9: EXAMPLE FREQUENCY SETTINGS
Divider
Frequency
0
48MHz
1
24MHz
2
16MHz
3
12MHz
4
9.6MHz
15
2.18MHz
2A
1.12MHz
 2014 - 2015 Microchip Technology Inc.
DS00001719D-page 363