MEC1322 Datasheet, PDF (73/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 4-5:
Offset
00h
04h
08h
RUNTIME REGISTER SUMMARY
Register Name
Power-Fail and Reset Status Register
MCHP Reserved
Clock Enable Register
4.7.1 POWER-FAIL AND RESET STATUS REGISTER
The Power-Fail and Reset Status Register collects and retains the VBAT RST and WDT event status when VCC1 is
unpowered.
Address ^00h
Bits
Description
Type
7 VBAT_RST
The VBAT RST bit is set to ‘1’ by hardware when a VBAT_POR is
detected. This is the register default value. To clear VBAT RST EC
firmware must write a ‘1’ to this bit; writing a ‘0’ to VBAT RST has no
affect.
6 Reserved
5 WDT
The WDT bit is asserted (‘1’) following a Watch-Dog Timer Forced
Reset (WDT Event). To clear the WDT bit EC firmware must write a
‘1’ to this bit; writing a ‘0’ to the WDT bit has no affect.
4:1 Reserved
0 DET32K_IN
0 = No clock detected on the XTAL[1:2] pins.
1= Clock detected on the XTAL[1:2] pins.
R/WC
RES
R/WC
RES
R
Default
1
Reset
Event
VBAT_P
OR
-
-
0
VBAT_P
OR
-
-
X
VBAT_P
OR
4.7.2 CLOCK ENABLE REGISTER
Address ^08h
Bits
Description
31:2 RESERVED
1 32K_EN
This bit controls the 32.768 KHz Crystal Oscillator as defined in
TABLE 4-6:.
0 XOSEL
This bit controls whether a crystal or single ended clock source is
used.
1= the 32.768 KHz Crystal Oscillator is driven by a single-ended
32.768 KHz clock source connected to the XTAL2 pin.
0= the 32.768 KHz Crystal Oscillator requires a 32.768 KHz parallel
resonant crystal connected between the XTAL1 and XTAL2 pins
(default).
Type
RES
R/W
R/W
Default
-
0b
Reset
Event
-
VBAT_P
OR
0b
VBAT_P
OR
APPLICATION NOTE: The XOSEL bit should be correctly configured by firmware before the 32K_EN bit is
assserted.
 2014 - 2015 Microchip Technology Inc.
DS00001719D-page 73