MEC1322 Datasheet, PDF (202/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 15-4: EC INTERRUPT STRUCTURE (CONTINUED)
Vector
27
28
29
30
31
Name
IRQ27
IRQ28
IRQ29
IRQ30
IRQ31
Link
Register
ILINK1
ILINK1
ILINK1
ILINK1
ILINK1
Priority
(Default)
level 1 (low)
level 1 (low)
level 1 (low)
level 1 (low)
level 1 (low)
Relative
Priority
L5
L4
L3
L2
L1
Byte
Offset
D8h
E0h
E8h
F0h
F8h
Note: IRQ Vector 31 is the highest L1 Priority
15.8.3 DISABLING INTERRUPTS
The Block Enable Clear Register and Block Enable Set Register should not be used for disabling and enabling interrupts
for software operations i.e., critical sections. The ARM enable disable mechanisms should be used.
15.9 EC-Only Registers
The configuration registers listed in EC-Only Register Summary table are for a single instance of the EC Interrupt Aggre-
gator. The addresses of each register listed in the summary table are defined as a relative offset to the host “Begin
Address” defined in the EC-Only Register Base Address Table.
TABLE 15-5: EC-ONLY REGISTER ADDRESS RANGE TABLE
Instance Name
Interrupt Aggregator
Instance
Number
0
Host
EC
Address Space
32-bit internal
address space
Begin Address
(Note 15-1)
4000_C000h
Note 15-1 The Begin Address indicates the location of the first register accessable at offset 00h in the Interrupt
Aggregator EC-Only address space.
TABLE 15-6:
Offset
00h
04h
08h
0Ch
14h
18h
1Ch
20h
28h
2Ch
30h
34h
3Ch
40h
44h
48h
EC-ONLY REGISTER SUMMARY
Register Name
GIRQ8 Source Register
GIRQ8 Enable Set Register
GIRQ8 Result Register
GIRQ8 Enable Clear Register
GIRQ9 Source Register
GIRQ9 Enable Set Register
GIRQ9 Result Register
GIRQ9 Enable Clear Register
GIRQ10 Source Register
GIRQ10 Enable Set Register
GIRQ10 Result Register
GIRQ10 Enable Clear Register
GIRQ11 Source Register
GIRQ11 Enable Set Register
GIRQ11 Result Register
GIRQ11 Enable Clear Register
DS00001719D-page 202
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