MEC1322 Datasheet, PDF (252/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Offset ^{See Note 20-5}
Bits
Description
Type
8 Output Buffer Type
R/W
0 = Push-Pull
1 = Open Drain
Note:
Unless explicitly stated otherwise, pins with (I/O/OD) or
(O/OD) in their buffer type column in the tables in are
compliant with the following Programmable OD/PP Multi-
plexing Design Rule: Each compliant pin has a program-
mable open drain/push-pull buffer controlled by the
Output Buffer Type bit in the associated Pin Control
Register. The state of this bit controls the mode of the
interface buffer for all selected functions, including the
GPIO function.
7 Edge Enable (edge_en)
R/W
0 = Edge detection disabled
1 = Edge detection enabled
Default
Note 20-5
Reset
Event
VCC1_R
ESET
Note 20-5 VCC1_R
ESET
Note: See Table 20-8, "Edge Enable and Interrupt Detection
Bits Definition".
6:4 Interrupt Detection (int_det)
R/W
The interrupt detection bits determine the event that generates a
GPIO_Event.
Note: See Table 20-8, "Edge Enable and Interrupt Detection
Bits Definition".
3:2 Power Gating Signals
R/W
The Power Gating Signals provide the GPIO pin Power Emulation
options. The pin will be tristated when the selected power well is off
(i.e., gated) as indicated.
Note 20-5 VCC1_R
ESET
Note 20-5 VCC1_R
ESET
The Emulated Power Well column defined in the Multiplexing Tables
in Section 1.5, "Pin Multiplexing," on page 19 indicates the emulation
options supported for each signal. The Signal Power Well column
defines the actual buffer power supply per function.
00 = VCC1 Power Rail
The output buffer is tristated when VCC1GD = 0.
01 = VCC2 Power Rail
The output buffer is tristated when PWRGD = 0.
10 = Reserved
11 = Reserved
1:0 PU/PD (PU_PD)
These bits are used to enable an internal pull-up.
00 = None
01 = Pull Up Enabled
10 = Pull Down Enabled (Note 20-6)
11 = None
R/W Note 20-5 VCC1_R
ESET
Note 20-5 See Section 20.7, "Pin Multiplexing Control," on page 248 for the offset and default values for each
GPIO Pin Control Register.
Note 20-6 The Pin Control Registers for GPIO111-GPIO117 and GPIO120, which are PCI_PIO buffer type pins,
do not have an internal pull-down. This configuration option has no effect on the pin.
DS00001719D-page 252
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