MEC1322 Datasheet, PDF (378/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
35.0 EC SUBSYSTEM REGISTERS
35.1 Introduction
This chapter defines a bank of registers associated with the EC Subsystem.
35.2 References
None
35.3 Interface
This block is designed to be accessed internally by the EC via the register interface.
35.4 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
35.4.1 POWER DOMAINS
TABLE 35-1: POWER SOURCES
Name
Description
VCC1
The EC Subsystem Registers are all implemented on this single power
domain.
35.4.2 CLOCK INPUTS
This block does not require any special clock inputs. All register accesses are synchronized to the host clock.
35.4.3 RESETS
TABLE 35-2: RESET SIGNALS
Name
VCC1_RESET
Description
This reset signal, which is an input to this block, resets all the logic and
registers to their initial default state.
35.5 Interrupts
This block does not generate any interrupt events.
35.6 Low Power Modes
The EC Subsystem Registers may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
When this block is commanded to sleep it will still allow read/write access to the registers.
35.7 Description
The EC Subsystem Registers block is a block implemented for aggregating miscellaneous registers required by the
Embedded Controller (EC) Subsystem that are not unique to a block implemented in the EC subsystem.
35.8 EC-Only Registers
TABLE 35-3: EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Address Space
Base Address (Note 35-1)
EC_REG_BANK
0
EC
32-bit internal
4000_FC00h
address space
Note 35-1 The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
DS00001719D-page 378
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