MEC1322 Datasheet, PDF (349/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Changing values in the PS2 CONTROL REGISTER at a rate faster than 2 MHz, may result in unpredictable behavior.
29.15.4 PS2 STATUS REGISTER
Offset ^08h
Bits
Description
31:8 Reserved
7 XMIT_START_TIMEOUT
Transmit Start Timeout.
Type
R
R/WC
Default
-
0h
Reset
Event
-
VCC1_R
ESET
0=No transmit start timeout detected
1=A start bit was not received within 25 ms following the transmit
start event. The transmit start bit time-out condition is also indicated
by the XMIT_TIMEOUT bit.
6 RX_BUSY
R
Receive Channel Busy.
0h
VCC1_R
ESET
0=The channel is actively receiving PS/2 data
1=The channel is idle
5 XMIT_TIME_OUT
Transmitter Idle.
R/WC
0h
VCC1_R
ESET
When the XMIT_TIMEOUT bit is set, the PS2_T/R bit is held clear,
the PS/2 channel’s CLK line is pulled low for a minimum of 300μs
until the PS/2 Status register is read. The XMIT_TIMEOUT bit is set
on one of three transmit conditions: when the transmitter bit time
(the time between falling edges) exceeds 300μs, when the transmit-
ter start bit is not received within 25ms from signaling a transmit start
event or if the time from the first bit (start) to the 10th bit (parity)
exceeds 2ms
4 XMIT_IDLE
R
Transmitter Idle.
0h
VCC1_R
ESET
0=The channel is actively transmitting PS/2 data. Writing the PS2
Transmit Buffer Register will cause the XMIT_IDLE bit to clear
1=The channel is not transmitting. This bit transitions from ‘0’ to ‘1’ in
the following cases:
The falling edge of the 11th CLK
XMIT_TIMEOUT is set
The PS2_T/R bit is cleared
The PS2_EN bit is cleared.
A low to high transition on this bit generates a PS2 Activity interrupt.
3 FE
Framing Error
R/WC
0h
VCC1_R
ESET
When receiving data, the stop bit is clocked in on the falling edge of
the 11th CLK edge. If the channel is configured to expect either a
high or low stop bit and the 11th bit is contrary to the expected stop
polarity, then the FE and REC_TIMEOUT bits are set following the
falling edge of the 11th CLK edge and an interrupt is generated.
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DS00001719D-page 349