MEC1322 Datasheet, PDF (382/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
36.0 TEST MECHANISMS
36.1 Introduction
This section defines the XNOR Chain for board test.
Other test mechanisms for the ARM are described in Chapter 7.0, "ARM M4F Based Embedded Controller".
36.2 XNOR Chain
36.2.1 OVERVIEW
The XNOR Chain test mode provides a means to confirm that all MEC1322 pins are in contact with the motherboard
during assembly and test operations.
An example of an XNOR Chain test structure is illustrated below in 36.2.3Figure 36-1. When the XNOR Chain test mode
is enabled all pins, except for the Excluded Pins shown in Section 36.2.2, are disconnected from their internal functions
and forced as inputs to the XNOR Chain. This allows a single input pin to toggle the XNOR Chain output if all other
input pins are held high or low. The XNOR Chain output is the Test Output Pin, pin 17: KSO04/GPIO103/TFDP_-
DATA/XNOR.
The tests that are performed when the XNOR Chain test mode is enabled require the board-level test hardware to con-
trol the device pins and observe the results at the XNOR Chain output pin; e.g., as described in Section 36.2.3, "Test
Procedure," on page 383.
36.2.2 EXCLUDED PINS
All pins in the pinout are included in the XNOR chain, except the following:
• Power Pins (VCC1, AVCC, VBAT, VREF_PECI)
• Ground Pins (VSS, AVSS, VSS_VBAT)
• CAP
• Crystal pins (XTAL1, XTAL2)
• Test Output Pin, pin 17: KSO04/GPIO103/TFDP_DATA/XNOR
• Test Port (JTAG_RST#, KSO02/GPIO101/JTAG_TDI, KSO03/GPIO102/JTAG_TDO,
KSO01/GPIO100/JTAG_TMS, and KSO00/GPIO000/JTAG_TCK)
FIGURE 36-1:
XNOR CHAIN TEST STRUCTURE
I/O#1
I/O#2
I/O#3
I/O#n
XNOR
Out
DS00001719D-page 382
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