MEC1322 Datasheet, PDF (87/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
5.8.4.6 AC/DC Specification Issue
All Serial IRQ agents must drive/sample SERIRQ synchronously related to the rising edge of LCLK. The SERIRQ pin
uses the electrical specification of the PCI bus. Electrical parameters will follow the PCI Local Bus Specification, Rev.
2.2 definition of “sustained tri-state.”
5.8.4.7 Reset and Initialization
The SERIRQ bus uses LRESET# as its reset signal and follows the PCI bus reset mechanism. The SERIRQ pin is tri-
stated by all agents while LRESET# is active. With reset, SERIRQ slaves and bridges are put into the (continuous) Idle
mode. The host controller is responsible for starting the initial SERIRQ cycle to collect system’s IRQ/Data default values.
The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SERIRQ
cycles. It is the host controller’s responsibility to provide the default values to the 8259’s and other system logic before
the first SERIRQ cycle is performed. For SERIRQ system suspend, insertion, or removal application, the host controller
should be programmed into Continuous (IDLE) mode first. This is to ensure the SERIRQ bus is in Idle state before the
system configuration changes.
5.8.4.8 SERIRQ Interrupts
The LPC Controller routes Logical Device interrupts onto SIRQ stream frames IRQ[0:15]. Routing is controlled by the
SIRQ Interrupt Configuration Registers. There is one SIRQ Interrupt Configuration Register for each accessible SIRQ
Frame (IRQ); all 16 registers are listed in Table 5-15, "SIRQ Interrupt Configuration Register Map".
The format for each SIRQ Interrupt Configuration Register is described in Section 5.9.2.1, "SIRQ Configuration Register
Format," on page 90. Each Logical Device can have up to two LPC SERIRQ interrupts. When the device is polled by
the host, each SIRQ frame routes the level of the Logical Device interrupt (selected by the corresponding SIRQ Interrupt
Configuration Register) to the SIRQ stream.
5.8.4.9 SERIRQ Routing
Each SIRQ Interrupt Configuration Register controls a series of multiplexers which route to a single Logical Device inter-
rupt as illustrated in FIGURE 5-6: SIRQ Routing Internal Logical Devices on page 88. The following table defines the
Serial IRQ routing for each logical device implemented in the chip.
TABLE 5-12: LOGICAL DEVICE SIRQ ROUTING
SIRQ Interrupt Configuration
Register
Logical Device Interrupt Source
SELECT
0
1
0
1
0
0
0
0
0
0
1
DEVICE
0
0
0
0
0
0
0
0
0
0
0
FRAME
0h
0h
1h
1h
3h
4h
5h
6h
7h
9h
9h
Logical Device
(Block Instance - Note 1:)
EMI
EMI
8042 Keyboard Controller
8042 Keyboard Controller
ACPI EC0
ACPI EC1
ACPI PM1
Legacy Port92/GateA20
UART 0
Mailbox
Mailbox
Interrupt Source
EC-to-Host
Host Event
KIRQ
MIRQ
EC_OBF
EC_OBF
N/A
N/A
UART
MBX_Host SIRQ
MBX_Host_SMI
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