MEC1322 Datasheet, PDF (348/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
29.15.2 PS2 RECEIVE BUFFER REGISTER
Offset ^00h
Bits
Description
31:8 Reserved
7:0 RECEIVE_DATA
Data received from a peripheral are recorded in this register.
Type
R
R
A transmission initiated by writing the PS2 Transmit Buffer Register
will not start until valid data in this register have been read and
RDATA_RDY has been cleared by hardware.
29.15.3
The Receive Buffer Register is initialized to FFh after a read or after
a Time-out has occurred.
PS2 CONTROL REGISTER
Offset ^00h
Bits
Description
31:6 Reserved
5:4 STOP
These bits are used to set the level of the stop bit expected by the
PS/2 channel state machine. These bits are therefore only valid
when PS2_EN is set.
Type
R
R/W
00b=Receiver expects an active high stop bit.
01b=Receiver expects an active low stop bit.
10b=Receiver ignores the level of the Stop bit (11th bit is not inter-
preted as a stop bit).
11b=Reserved.
3:2 PARITY
R/W
These bits are used to set the parity expected by the PS/2 channel
state machine. These bits are therefore only valid when PS2_EN is
set.
00b=Receiver expects Odd Parity (default).
01b=Receiver expects Even Parity.
10b=Receiver ignores level of the parity bit (10th bit is not interpreted
as a parity bit).
11b=Reserved
1 PS2_EN
R/W
PS/2 Enable.
0=The PS/2 state machine is disabled. The CLK pin is driven low and
the DATA pin is tri-stated.
1=The PS/2 state machine is enabled, allowing the channel to per-
form automatic reception or transmission, depending on the
state of PS2_T/R.
0 PS2_T/R
R/W
PS/2 Transmit/Receive
0=The P2/2 channel is enabled to receive data.
1=The PS2 channel is enabled to transmit data.
Default
-
FFh
Reset
Event
-
VCC1_R
ESET
Default
-
0h
Reset
Event
-
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
DS00001719D-page 348
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