MEC1322 Datasheet, PDF (16/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
1.4.7 FAN TACHOMETER AND PWM INTERFACE
TABLE 1-11: FAN TACHOMETER AND PWM INTERFACE
PWM & TACHOMETER
Pin Ref. Number Signal Name
92
TACH1
101
TACH2PWM_IN
120
PWM0
118
PWM1
78
PWM3
121
TACH2PWM_OUT
Description
Fan Tachometer Input 2
Tach input to RPM-Based Fan Speed Control
Algorithm
Pulse Width Modulator Output 0
Pulse Width Modulator Output 1
Pulse Width Modulator Output 3
Pulse Width Modulator Output from RPM
Based Fan Speed Control Algorithm
1.4.8 GENERAL PURPOSE I/O INTERFACE
TABLE 1-12: GPIO INTERFACE
GPIO Interface
Pin Ref. Number Signal Name
See Pin Configuration
Table
GPIO
Description
General Purpose Input Output Pins
(6 Pins)
Notes
Notes
Note 12
Note: No GPIO pin should be left floating in a system. If a GPIO pin is not in use, it should be either tied high, tied
low, or pulled to either power or ground through a resistor.
1.4.9 MISCELLANEOUS FUNCTIONS
TABLE 1-13: MISCELLANEOUS FUNCTIONS
MISC Functions
Pin Ref. Number
102
122
113
114
115
78
16
17
60
72
77
85
17
Signal Name
A20M
KBRST
LED0
LED1
LED2
LED3
TFDP_CLK
TFDP_DATA
nRESET_OUT
VCC_PWRGD
VCC1_RST#
RSMRST#
XNOR
Description
KBD GATEA20 Output
CPU_RESET
LED (Bllinking/Breathing PWM) Output 0
LED (Bllinking/Breathing PWM) Output 1
LED (Bllinking/Breathing PWM) Output 2
LED (Bllinking/Breathing PWM) Output 3
Trace FIFO debug port - clock
Trace FIFO debug port - data
EC-driven External System Reset
System Main Power Indication
Reset Generator Output
Resume Reset Output
Test Output
(13 Pins)
Notes
Note 6
Note 6
Note 1: The KBRST pin function is the output of CPU_RESET described in Section 11.11.2, "CPU_RESET Hard-
ware Speed-Up," on page 151.
2: The nRESET_OUT pin function is an external output signal version of the internal signal nSIO_RESET. See
the iRESET_OUT bit in the Power Reset Control (PWR_RST_CTRL) Register on page 71 and nSIO_RE-
SET in Table 3-7, “Definition of Reset Signals,” on page 52.
3: XNOR is a push-pull output. This function is not configured through the associated GPIO Pin Control Reg-
ister; however the drive strength is configured through the associated GPIO Pin Control Register 2.
DS00001719D-page 16
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