MEC1322 Datasheet, PDF (125/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
9.10.2 EC-TO-HOST MAILBOX REGISTER
Offset ^01h
Bits
Description
7:0 EC_HOST_MBOX
8-bit mailbox used communicate information from the embedded
controller to the system host. Writing this register generates an
event to notify the system host.
Type
R/W
The system host has the option of clearing some or all of the bits in
this register. This is dependent on the protocol layer implemented
using the EMI Mailbox. The embedded controller must know this
protocol to determine the meaning of the value that will be reported
on a read.
9.10.3
This bit field is aliased to EC_HOST_MBOX bit field in the EC-to-
HOST Mailbox Register.
MEMORY BASE ADDRESS 0 REGISTER
Offset ^04h
Bits
Description
Type
31:2 MEMORY_BASE_ADDRESS_0
R/W
This memory base address defines the beginning of region 0 in the
Embedded Controller’s 32-bit internal address space. Memory allo-
cated to region 0 is intended to be shared between the Host and the
EC. The region defined by this base register is used when bit 15 of
the EC Address Register is 0. The access will be to a memory loca-
tion at an offset defined by the EC_Address relative to the beginning
of the region defined by this register. Therefore, a read or write to the
memory that is triggered by the EC Data Register will occur at Mem-
ory_Base_Address_0 + EC_Address.
1:0 Reserved
R
9.10.4 MEMORY READ LIMIT 0 REGISTER
Offset ^08h
Bits
Description
15 Reserved
14:2 MEMORY_READ_LIMIT_0
Whenever a read of any byte in the EC Data Register is attempted,
and bit 15 of EC_Address is 0, the field EC_Address[14:2] in the
EC_Address_Register is compared to this field. As long as EC_Ad-
dress[14:2] is less than this field the EC_Data_Register will be
loaded from the 24-bit internal address space.
1:0 Reserved
Type
R
R/W
R
Default
0h
Reset
Event
VCC1_R
ESET
Default
0h
Reset
Event
VCC1_R
ESET
-
-
Default
-
0h
Reset
Event
-
VCC1_R
ESET
-
-
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DS00001719D-page 125