MEC1322 Datasheet, PDF (264/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
21.9 EC-Only Registers
The DMA Controller consists of a Main Block and a number of Channels. Table 21-9, "Main EC-Only Register Summary"
lists the registers in the Main Block and Table 21-10, "Channel EC-Only Register Summary" lists the registers in each
channel. The addresses of each register listed in these tables are defined as a relative offset to the “Base Address”
defined in the EC-Only Register Base Address Table. The Base Address for the Main Block and each Channel is defined
in the table:
TABLE 21-8: EC-ONLY REGISTER BASE ADDRESS TABLE
Instance Name
Channel
Number
Host
Address Space
Base Address
DMA Controller
Main Block
EC
32-bit internal
address space
4000_2400h
DMA Controller
0
EC
32-bit internal
address space
4000_2410h
DMA Controller
1
EC
32-bit internal
address space
4000_2430h
DMA Controller
2
EC
32-bit internal
address space
4000_2450h
DMA Controller
3
EC
32-bit internal
address space
4000_2470h
DMA Controller
4
EC
32-bit internal
address space
4000_2490h
DMA Controller
5
EC
32-bit internal
address space
4000_24B0h
DMA Controller
6
EC
32-bit internal
address space
4000_24D0h
DMA Controller
7
EC
32-bit internal
address space
4000_24F0h
DMA Controller
8
EC
32-bit internal
address space
4000_2510h
DMA Controller
9
EC
32-bit internal
address space
4000_2530h
DMA Controller
10
EC
32-bit internal
address space
4000_2550h
DMA Controller
11
EC
32-bit internal
4000_2570h
address space
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 21-9:
Offset
00h
04h
MAIN EC-ONLY REGISTER SUMMARY
REGISTER NAME (Mnemonic)
DMA Main Control
DMA Data Packet
DS00001719D-page 264
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