MEC1322 Datasheet, PDF (410/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 38-15: PS/2 CHANNEL RECEIVE TIMING DIAGRAM PARAMETERS
Name
Description
MIN
TYP
t1 The PS/2 Channel’s CLK and DATA lines
are floated following PS2_EN=1 and
PS2_T/R=0.
t2 Period of CLK
60
t3 Duration of CLK high (active)
30
t4 Duration of CLK low (inactive)
t5 DATA setup time to falling edge of CLK.
1
MEC1322 samples the data line on the fall-
ing CLK edge.
t6 DATA hold time from falling edge of CLK.
2
MEC1322 samples the data line on the fall-
ing CLK edge.
t7 Duration of Data Frame. Falling edge of
Start bit CLK (1st clk) to falling edge of Par-
ity bit CLK (10th clk).
t8 Falling edge of 11th CLK to RDATA_RDY
asserted.
t9 Trailing edge of the EC’s RD signal of the
Receive Register to RDATA_RDY bit de-
asserted.
t10 Trailing edge of the EC’s RD signal of the
Receive Register to the CLK line released
to high-Z.
t11 PS2_CLK is "Low" and PS2_DATA is "Hi-
Z" when PS2_EN is de-asserted.
t12 RDATA_RDY asserted an interrupt is gen-
erated.
MAX
1000
302
151
2.002
1.6
500
Units
ns
µs
ms
µs
ns
DS00001719D-page 410
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