MEC1322 Datasheet, PDF (216/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
1= Writing a one will enable respective IRQi.
Reading always returns the current value of the IRQ i VECTOR ENABLE bit. The state of the IRQ i VECTOR ENABLE
bit is determined by the corresponding IRQ i Vector Enable Set bit and the IRQ i Vector Enable Clear bit. (0=disabled,
1-enabled)
15.9.18 BLOCK ENABLE CLEAR REGISTER
Offset
POWER
BIT
TYPE
BIT NAME
BIT
TYPE
BIT NAME
BIT
TYPE
BIT NAME
BIT
TYPE
BIT NAME
204h
VCC1
D31
R
D23
R/WC
D15
R/WC
D7
R
D30
R
D22
R/WC
D14
R/WC
D6
R
32-bit
0000_0000h
D29
D28
D27
D26
R
R
R
R
Reserved
D21
R/WC
D20
R/WC
D19
R/WC
D18
R/WC
IRQ Vector Enable Clear [23:16]
D13
D12
D11
D10
R/WC R/WC R/WC R/WC
IRQ Vector Enable Clear [15:8]
D5
D4
D3
D2
R
R
R
R
Reserved
Size
VCC1_RESET
Default
D25
D24
R
R
D17
R/WC
D16
R/WC
D9
R/WC
D8
R/WC
D1
D0
R
R
IRQ Vector Enable Clear[31:0]
Each IRQ Vector can be individually disabled to assert an interrupt event to the EC.
0= Writing a zero has no effect.
1= Writing a one will disable respective IRQi vector.
Reading always returns the current value of the IRQ i VECTOR ENABLE bit. The state of the IRQ i VECTOR ENABLE
bit is determined by the corresponding IRQ i Vector Enable Set bit and the IRQ i Vector Enable Clear bit. (0=disabled,
1-enabled)
15.9.19 BLOCK IRQ VECTOR REGISTER
Offset
POWER
208h
VCC1
BIT
TYPE
BIT NAME
BIT
TYPE
D31
D30
D29
R
R
R
D23
D22
D21
R
R
R
32-bit
0000_0000h
D28
D27
D26
R
R
R
Reserved
D20
D19
D18
R
R
R
Size
VCC1_RESET
Default
D25
D24
R
R
D17
D16
R
R
DS00001719D-page 216
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