MEC1322 Datasheet, PDF (53/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 3-7: DEFINITION OF RESET SIGNALS (CONTINUED)
Reset
Description
Source
WDT_RESET
Internal WDT Reset signal. This signal resets
VCC1 powered registers with the exception of
the WDT Event Count register. Note that the
glitch protect circuits do not activate on a WDT
reset. WDT_RESETdoes not reset VBAT
registers or logic.
A WDT_RESET is asserted by a WDT Event.
Note:
This event is indicated by the WDT
bit in the Power-Fail and Reset Sta-
tus Register
EC_PROC_
RESET
Internal reset signal to reset the processor in the
EC Subsystem.
An EC_PROC_ RESET is a stretched version of
the VCC1_RESET. This reset asserts at the
same time that VCC1_RESET asserts and is
held asserted for 1ms after the VCC1_RESET
deasserts.
Note 3-8
If the LRESET# pin is assigned to the GPIO function rather than LRESET#, the internal LRESET#
signal is gated low, and therefore the nRESET_OUT function will not operate properly.
3.6.1 INTEGRATED VCC1 POWER ON RESET (VCC1_RST#)
The VCC1_RST# pin is used to control the power up sequence for external devices. The VCC1_RST# timing is shown
in Section 38.1.1, "VCC1_RST# Timing," on page 397.
The following summarizes the operation of the VCC1_RST# signal.
• The VCC1_RST# pin is both a reset input and an output to the system.
• The VCC1_RST# output provides a POR reset during power up transition
• The VCC1_RST# output has Output Pin Glitch Protection
• The VCC1_RST# output stretches an external driven reset by 1ms (typ).
• The VCC1_RST# input detects an externally driven reset and places the MEC1322 into a VCC1 POR state.
The VCC1_RST# is an open drain pin. An external pull-up is required for the VCC1_RST# signal to be high.
Note: The external pull-up on the VCC1_RST# pin must be chosen to meet the timing in Table 38-2,
“VCC1_RST# Rise Time,” on page 397.
The following sequence illustrates the interaction between the internally and externally driven assertion of VCC1_RST#:
1. The Integrated VCC1 Power On Reset Generator insures VCC1_RST# is driven low during a VCC1 POR from
VCC1 = 1V to 2.4V (typ) without glitches.
2. The VCC1_RST# pin is driven low during the POR transition until VCC1 > 2.4V (typ) and then the VCC1_RST#
pin remains low afterwards for 1ms (typ) delay window. The VCC1_RST# input is not examined during the 1ms
(typ) delay window; therefore, the system input and/or the external pin termination may be modified (i.e. drive it
low, let it float, etc.)
- The VCC1_RST# input is not examined during the POR transition while VCC1 < 2.4V (typ); therefore, the
system input to the VCC1_RST# pin may modify the output termination (i.e. drive it low, let it float, etc.)
3. The VCC1_RST# pin is driven low during the 1ms (typ) delay window. The MEC1322 is in the VCC1_POR state
during this time.
4. After the 1ms (typ) window, the VCC1_RST# pin open drain output from the MEC1322 is not driven/released.
The strap option pins are sampled at this time.
5. The MEC1322 will remain in the VCC1 POR for 2.65us (min) after the VCC1_RST# pin is released The
VCC1_RST# input pin is ignored during this time.
6. The VCC1_RST# pin input is sampled at 2.65us (min) after the VCC1_RST# pin is released.
- If the VCC1_RST# pin is high when sampled, then the EC starts executing.
- If the VCC1_RST# pin is low when sampled, the pin is being driven externally (i.e., the system is forcing a
reset):
- The VCC1_RST# pin is driven low for 1ms (typ), then sampled at 2.65us (min) after the VCC1_RST# pin is
released (see step 3).
 2014 - 2015 Microchip Technology Inc.
DS00001719D-page 53