MEC1322 Datasheet, PDF (183/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
14.11.1 RECEIVE BUFFER REGISTER
Offset ^{0h (DLAB=0)}
Bits
Description
7:0 RECEIVED_DATA
This register holds the received incoming data byte. Bit 0 is the least
significant bit, which is transmitted and received first. Received data
is double buffered; this uses an additional shift register to receive the
serial data stream and convert it to a parallel 8 bit word which is
transferred to the Receive Buffer register. The shift register is not
accessible.
Type
R
Default
0h
Reset
Event
RESET
14.11.2 TRANSMIT BUFFER REGISTER
Offset ^{0h (DLAB=0)}
Bits
Description
7:0 TRANSMIT_DATA
This register contains the data byte to be transmitted. The transmit
buffer is double buffered, utilizing an additional shift register (not
accessible) to convert the 8 bit data word to a serial format. This shift
register is loaded from the Transmit Buffer when the transmission of
the previous byte is complete.
Type
W
Default
0h
Reset
Event
RESET
14.11.3 PROGRAMMABLE BAUD RATE GENERATOR LSB REGISTER
Offset ^{00h (DLAB=1)}
Bits
Description
7:0 BAUD_RATE_DIVISOR_LSB
See Section 14.9.1, "Programmable Baud Rate".
Type
R/W
Default
0h
Reset
Event
RESET
14.11.4 PROGRAMMABLE BAUD RATE GENERATOR MSB REGISTER
Offset ^{01h (DLAB=1)}
Bits
Description
Type
7 BAUD_CLK_SEL
R/W
1=If CLK_SRC is ‘0’, the baud clock is derived from the 1.8432MHz_-
Clk. If CLK_SRC is ‘1’, this bit has no effect
1=If CLK_SRC is ‘0’, the baud clock is derived from the 24MHz_Clk.
If CLK_SRC is ‘1’, this bit has no effect
6:0 BAUD_RATE_DIVISOR_MSB
R/W
See Section 14.9.1, "Programmable Baud Rate".
Default
0h
Reset
Event
RESET
0h
RESET
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DS00001719D-page 183