MEC1322 Datasheet, PDF (56/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Note 3-10 MCHP Reserved bits in the sleep_en registers must be written to 1 in order for the chip to be put
into sleep mode.
3.9.2 CHIP CLOCK REQUIRED STATUS REGISTERS (CHIP_CLK_REQ_STS)
Offset ^04h
Bits
31:2 RESERVED
1 MCHP Reserved
0 MCHP Reserved
Description
Type
RES
R
R
Default
Reset
Event
0h
VCC1_R
ESET
-
VCC1_R
ESET
3.9.3 EC SLEEP ENABLE REGISTER (EC_SLP_EN)
Offset ^08h
Bits
Description
31 TIMER16_1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note 3-11 on page 57.
30 TIMER16_0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note 3-11 on page 57.
29 EC_REG_BANK Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
28:23 RESERVED
22 PWM3 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
21 PWM2 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
20 PWM1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
19:12 RESERVED
11 TACH1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
10 SMB0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
9 WDT Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
Type
R/W
Default
0h
Reset
Event
VCC1_R
ESET
R/W
0h
VCC1_R
ESET
R/W
RES
R/W
R/W
R/W
RES
R/W
R/W
R/W
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
DS00001719D-page 56
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