MEC1322 Datasheet, PDF (237/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
19.11.10 YEAR REGISTER
Offset ^09h
Bits
Description
7:0 YEAR
Displays the number of the year in the current century, in the range 0
(year 2000) through 99 (year 2099). Presentation may be selected as
binary or BCD, depending on the DM bit in Register B. Values written
must also use the format defined by the current setting of the DM bit.
Type
R/W
Default
00h
Reset
Event
RTC_R
ST
19.11.11 REGISTER A
Offset ^0Ah
Bits
Description
Type
7 UPDATE_IN_PROGRESS
R
‘0’ indicates that the Time and Date registers are stable and will not be
altered by hardware soon. ‘1’ indicates that a hardware update of the
Time and Date registers may be in progress, and those registers
should not be accessed by the host program. This bit is set to ‘1’ at a
point 488us (16 cycles of the 32K clock) before the update occurs, and
is cleared immediately after the update. See also the Update-Ended
Interrupt, which provides more useful status.
6:4 DIVISION_CHAIN_SELECT
R/W
This field provides general control for the Time and Date register
updating logic.
11xb=Halt counting. The next time that 010b is written, updates will
begin 500ms later.
010b=Required setting for normal operation. It is also necessary to set
the Block Enable bit in the RTC Control Register to ‘1’ for counting
to begin
000b=Reserved. This field should be initialized to another value before
Enabling the block in the RTC Control Register
Other values Reserved
3:0 RATE_SELECT
R/W
This field selects the rate of the Periodic Interrupt source. See
Table 19-8
Default
0b
Reset
Event
RTC_R
ST
000b
RTC_R
ST
0h
RTC_R
ST
TABLE 19-8:
RS (hex)
0
1
2
3
4
5
6
REGISTER A FIELD RS: PERIODIC INTERRUPT SETTINGS
Interrupt Period
Never Triggered
3.90625 ms
7.8125 ms
122.070 us
244.141 us
488.281 us
976.5625 us
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DS00001719D-page 237