MEC1322 Datasheet, PDF (79/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
The LPC Controller claims only LPC transactions targeted for one of its peripherals. Section 5.8.2, on page 81,
describes the mechanism for Claiming and Forwarding Transactions for Supported LPC Cycles. LPC transactions may
be used to configure the chip and to access registers during operation. The mechanism to configure the chip is
described in Section 5.8.3, "Configuration Port," on page 83.
LPC memory cycles may also be used to access the Base Address Registers of certain devices.
Once configured, the LPC peripherals implemented as logical devices on chip may use the SERIRQ to notify the host
of an event. See Section 5.8.4, "Serial IRQs," on page 84.
5.8.1 LPC CONTROLLER DESCRIPTION
The following sections qualify the LPC features implemented according to the LPC Specification.
5.8.1.1 Cycle Types Supported
The following cycle types are supported by the LPC Interface Controller. All other cycles that it does not support are
ignored.
TABLE 5-8: LPC CYCLE TYPES SUPPORTED
Cycle Type
I/O Read
I/O Write
Memory Read
Memory Write
Transfer Size
1 byte
1 byte
1 byte
1 byte
When the LPC Controller detects a transaction targeted for this device it claims and forwards that transaction as defined
in Section 5.8.2, "Claiming and Forwarding Transactions for Supported LPC Cycles," on page 81.
LPC I/O CYCLES
The system host may use LPC I/O cycles to read/write the I/O mapped configuration and runtime registers implemented
in this device. See the Intel® Low Pin Count (LPC) Interface Specification, v1.1, Section 5.2 for definition of LPC I/O
Cycles.
LPC MEMORY CYCLES
The system host may use LPC memory cycles to access memory mapped registers implemented in this device. See
the Intel® Low Pin Count (LPC) Interface Specification, v1.1, Section 5.1 for definition of LPC Memory Cycles.
5.8.1.2 LAD[3:0] Fields
The LAD[3:0] signals support multiple fields for each protocol as defined in section 4.2.1 LAD[3:0] of the Intel® Low Pin
Count (LPC) Interface Specification, v1.1. The following sections further qualify the fields supported.
WAIT SYNCS ON LPC
LPC transactions that access registers located on the device require a minimum of two wait SYNCs on the LPC bus.
The number of SYNCs may be larger if the internal bus is in use by the embedded controller, of if the data referenced
by the host is not present in a register. The device always uses Long Wait SYNCs, rather than Short Wait SYNCs, when
responding to an LPC bus request.
Note: All LPC transactions are synchronized to the LCLK and will complete with a maximum of 8 wait states,
unless otherwise noted.
ERROR SYNCS ON LPC
The device does not issue ERROR SYNC cycles.
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