MEC1322 Datasheet, PDF (249/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 20-7: REGISTER SUMMARY (CONTINUED)
Offset
Register Name
284h
Output GPIO[040:076]
(Note 20-3)
288h
Output GPIO[100:127]
(Note 20-3)
28Ch
Output GPIO[140:176]
(Note 20-3)
290h
Output GPIO[200:236]
(Note 20-3)
300h
Input GPIO[000:036]
(Note 20-3)
304h
Input GPIO[040:076]
(Note 20-3)
308h
Input GPIO[100:127]
(Note 20-3)
30Ch
Input GPIO[140:176]
(Note 20-3)
310h
Input GPIO[200:236]
(Note 20-3)
500h - 51Ch GPIO000-GPIO007 Pin Control Register 2
520h - 53Ch GPIO010-GPIO017 Pin Control Register 2
540h - 55Ch GPIO020-GPIO027 Pin Control Register 2
560h - 578h GPIO030-GPIO036 Pin Control Register 2
580h - 59Ch GPIO040-GPIO047 Pin Control Register 2
5A0h - 5BCh GPIO050-GPIO057 Pin Control Register 2
5C0h - 5DCh GPIO060-GPIO067 Pin Control Register 2
5E0h - 5FCh GPIO100-GPIO107 Pin Control Register 2
600h
GPIO110 Pin Control Register 2
604h - 623h MCHP Reserved (Note 20-4)
624h - 63Ch GPIO121-GPIO127 Pin Control Register 2
640h - 658h GPIO130-GPIO136 Pin Control Register 2
660h - 67Ch GPIO140-GPIO147 Pin Control Register 2
680h - 69Ch GPIO150-GPIO157 Pin Control Register 2
6A0h - 6B4h GPIO160-GPIO165 Pin Control Register 2
720h - 730h GPIO200-GPIO204 Pin Control Register 2
738h
GPIO206 Pin Control Register 2
740h - 744h GPIO210-GPIO211 Pin Control Register 2
Note 20-3 The GPIO input and output registers are LPC I/O accessible via Region 0 of the EMI block. This
access is defined in the EMI Protocols chapter of the firmware specification.
Note 20-4 There is no Pin Control Register 2 for GPIO111-GPIO117 and GPIO120, which are PCI_PIO buffer
type pins. The drive strength and slew rate are not configurable on these pins.
 2014 - 2015 Microchip Technology Inc.
DS00001719D-page 249