MEC1322 Datasheet, PDF (344/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
29.6 Host Interface
The registers defined for the Keyboard Scan Interface are accessible by the various hosts as indicated in Section 29.15,
"EC-Only Registers".
29.7 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
29.7.1 POWER DOMAINS
TABLE 29-2:
POWER SOURCES
Name
VCC1
29.7.2 CLOCK INPUTS
Description
The logic and registers implemented in this block are powered by this
power well.
TABLE 29-3: CLOCK INPUTS
Name
48 MHz Ring Oscillator
2 MHz Clock
29.7.3 RESETS
Description
This is the clock source for PS/2 Interface logic.
The PS/2 state machine is clocked using the 2 MHz clock.
TABLE 29-4: RESET SIGNALS
Name
VCC1_RESET
Description
This signal resets all the registers and logic in this block to their default
state.
29.8 Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 29-5:
EC INTERRUPTS
Source
PW2_x
PS2_x_WK
Description
Interrupt request to the Interrupt Aggregator for PS2 controller instance
x, based on PS2 controller activity. Section 29.15.4, "PS2 Status
Register" defines the sources for the interrupt request.
Wake-up request to the Interrupt Aggregator’s wake-up interface for PS2
port x.
In order to enable PS2 wakeup interrupts, the pin control registers for the
PS2DAT pin must be programmed to Input, Falling Edge Triggered, non-
inverted polarity detection.
29.9 Low Power Modes
The PS/2 Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
The PS2 interface will only sleep while the PS2 is disabled or in Rx mode with no traffic on the bus.
29.10 Description
Each EC PS/2 serial channels use a synchronous serial protocol to communicate with the auxiliary device. Each PS/2
channel has Clock and Data signal lines. The signal lines are bi-directional and employ open drain outputs capable of
sinking 12m, as required by the PS/2 specification. A pull-up resistor, typically 10K, is connected to both lines. This
allows either the EC PS/2 logic or the auxiliary device to drive the lines. Regardless of the drive source, the auxiliary
DS00001719D-page 344
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