MEC1322 Datasheet, PDF (361/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
5. The Master state machine loads the Data Register, issues a BUSY Bit Clear interrupt and clears the BUSY bit to
‘0’.
6. Software, after either receiving the Bit Clear interrupt, or polling the BUSY bit until it is ‘0’, checks the BC_ERR
bit in the Status Register.
7. Software can now read the Data Register which contains the valid data if there was no BC Bus error.
8. If a Bus Error occurs, firmware must issue a soft reset by setting the RESET bit in the Status Register to ‘1’.
9. The read can re-tried once BUSY is cleared.
Note: Steps 3 thorough 7 should be completed as a contiguous sequence. If not the interface could be presenting
incorrect data when software thinks it is accessing a valid register read.
31.10.2 BC-LINK MASTER WRITE OPERATION
1. Software starts by checking the status of the BUSY bit in the BC-Link Status Register. If the BUSY bit is ‘0’, pro-
ceed. If BUSY is ‘1’, firmware must wait until it is ‘0’.
2. Software writes the address of the register to be written into the BC-Link Address Register.
3. Software writes the data to be written into the addressed register in to the BC-Link Data Register.
4. The write to the Data Register starts the BC_Link write operation. The Master state machine sets the BUSY bit.
5. The BC-Link Master Interface transmits the write request packet.
6. When the write request packet is received by the BC-Link companion, the CRC is checked and data is written to
the addressed companion register.
7. The companion sends an ACK if the write is completed. A time-out will occur approximately 16 BC-Link clocks
after the packet is sent by the Master state machine. If a time-out occurs, the state machine will set the BC_ERR
bit in the Status Register to ‘1’ approximately 48 clocks later and then clear the BUSY bit.
8. The Master state machine issues the Bit Clear interrupt and clears the BUSY bit after receiving the ACK from the
Companion
9. If a Bus Error occurs, firmware must issue a soft reset by setting the RESET bit in the Status Register to ‘1’.
10. The write can re-tried once BUSY is cleared.
31.11 EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the BC-Link Master interface.
The addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in
the EC-Only Register Base Address Table.
TABLE 31-7: EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Address Space
Base Address (Note 31-1)
BC-LINK
0
EC
32-bit internal
4000_BC00h
address space
Note 31-1 The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
TABLE 31-8: EC-ONLY REGISTER SUMMARY
Register Name
EC Offset
BC-Link Status Register
00h
BC-Link Address Register
04h
BC-Link Data Register
08h
BC-Link Clock Select Register
0Ch
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DS00001719D-page 361