MEC1322 Datasheet, PDF (204/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 15-6: EC-ONLY REGISTER SUMMARY (CONTINUED)
Offset
Register Name
12Ch
GIRQ23 Source Register
130h
GIRQ23 Enable Set Register
134h
GIRQ23 Result Register
138h
GIRQ23 Enable Clear Register
200h
Block Enable Set Register
204h
Block Enable Clear Register
208h
Block IRQ Vector Register
All of the GIRQx Source, Enable, and Result registers have the same format. The following tables define the generic
format for each of these registers. The bit definitions are defined in the sections that follow.
Note:
The behavior of the enable bit controlled by the GIRQx Enable Set and GIRQx Enable Clear Registers, the
GIRQx Source bit, and the GIRQx Result bit are illustrated in Section 15.8.1, "WAKE Generation," on
page 194.
TABLE 15-7:
Offset
Power
GIRQX SOURCE REGISTER
-
VCC1
32-bit
0000_0000h
Size
VCC1_RESET
Default
Bit
D31
D30
D29
•• •
D2
D1
D0
Type
R
R/WC except for reserved bits, which are R
Bit Name
Reserved
See Tables in the following subsections
The R/WC bits are sticky status bits indicating the state of interrupt source before the interrupt enable bit.
TABLE 15-8: GIRQX ENABLE SET REGISTER
Offset
-
32-bit
Size
POWER
VCC1
0000_0000h
VCC1_RESET
Default
BIT
D31
D30
D29
•• •
D2
D1
D0
TYPE
R
R/WS except for reserved bits, which are R
BIT NAME
Reserved
GIRQ Enable Set [31:0]
See Tables in the following subsections
Each GIRQx bit can be individually enabled to assert an interrupt event.
0= Writing a zero has no effect.
1= Writing a one will enable respective GIRQx.
Reading always returns the current value of the GIRQx ENABLE bit. The state of the GIRQx ENABLE bit is determined
by the corresponding GIRQx Enable Set bit and the GIRQx Enable Clear bit. (0=disabled, 1-enabled)
DS00001719D-page 204
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