MEC1322 Datasheet, PDF (20/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
1.5.1 VCC2 POWER DOMAIN EMULATION
The System Runtime Supply power VCC2 is not connected to the MEC1322. The VCC_PWRGD signal is used to indi-
cate when power is applied to the System Runtime Supply.
Pin signal functions with VCC2 power domain emulation are documented in the Multiplexing Tables as “Signal Power
Well“= VCC1 and “Emulated Power Well” = VCC2. These pins are powered by VCC1 and controlled by the VCC_P-
WRGD signal input. Outputs on VCC2 power domain emulation pin signal functions are tri-stated when VCC_PWRGD
is not asserted and are functional when VCC_PWRGD is active. Inputs on VCC2 power domain emulation pin signal
functions are gated according as defined by the Gated State column in the following tables.
Power well emulation for GPIOs and for signals that are multiplexed with GPIO signals is controlled by the Power Gating
Signals field in the GPIO Pin Control Register.
1.5.2 MULTIPLEXING TABLES
In the following tables, the columns have the following meanings:
MUX
If the pin has an associated GPIO, then the MUX column refers to the Mux Control field in the GPIO Pin Control Register.
Setting the Mux Control field to value listed in the row will configure the pin for the signal listed in the Signal column on
the same row. The row marked “Default” is the setting that is assigned on system reset.
If there is no GPIO associated with a pin, then the pin has a single function.
Signal
This column lists the signals that can appear on each pin, as configured by the MUX control.
Buffer Type
Pin buffer types are defined in Table 37-4, “DC Electrical Characteristics,” on page 391.
Note that all GPIO pins are of buffer type PIO, which may be configured as input/output, push-pull/OD etc. via the GPIO
Pin Control Register and Pin Control Register 2. There are some pins where the buffer type is configured by the alternate
function selection, in which case that buffer type is shown in this column.
Default Operation
This column gives the pin behavior following the power-up of VCC1. All GPIO pins are programmable after this event.
This default pin behavior corresponds to the row marked “Default” in the MUX column.
Note: An internal pull-up resistor is indicated by (PU) and and internal pull-down is indicated by (PD). These are
configured via the GPIO Pin Control Register.
Signal Power Well
This column defines the power well that powers the pin.
Emulated Power Well
Power well emulation for GPIOs and for signals that are multiplexed with GPIO signals is controlled by the Power Gating
Signals field in the GPIO Pin Control Register.
Power well emulation for signals that are not multiplexed with GPIO signals is defined by the entries in this column.
See Section 1.5.1, "VCC2 Power Domain Emulation".
Note: The Glitch Protected POR Drive Low Pins are configured as “always on”, as indicated by “ON” in this col-
umn.
Gated State
This column defines the internal value of an input signal when either its emulated power well is inactive or it is not
selected by the GPIO alternate function MUX. A value of “No Gate” means that the internal signal always follows the
pin even when the emulated power well is inactive.
Note: Gated state is only meaningful to the operation of input signals. A gated state on an output pin defines the
internal behavior of the GPIO MUX and does not imply pin behavior.
DS00001719D-page 20
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