MEC1322 Datasheet, PDF (143/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
10.13.6 EC2OS DATA EC BYTE 1 REGISTER
This register is aliased; see ACPI-OS DATA BYTES[3:0] on page 135, OS2EC DATA BYTES[3:0] on page 141, and
EC2OS DATA BYTES[3:0] on page 142 for detailed description of access rules.
Offset ^101h
Bits
Description
Type
Default
Reset
Event
7:0 EC2OS_DATA_BYTE_1
This is byte 1 of the 32-bit EC2OS DATA BYTES[3:0].
R/W
0h
VCC1_R
ESET
10.13.7 EC2OS DATA EC BYTE 2 REGISTER
This register is aliased; see ACPI-OS DATA BYTES[3:0] on page 135, OS2EC DATA BYTES[3:0] on page 141, and
EC2OS DATA BYTES[3:0] on page 142 for detailed description of access rules.
Offset ^102h
Bits
Description
7:0 EC2OS_DATA_BYTE_2
This is byte 2 of the 32-bit EC2OS DATA BYTES[3:0].
Type
R/W
Default
0h
Reset
Event
VCC1_R
ESET
10.13.8 EC2OS DATA EC BYTE 3 REGISTER
This register is aliased; see ACPI-OS DATA BYTES[3:0] on page 135, OS2EC DATA BYTES[3:0] on page 141, and
EC2OS DATA BYTES[3:0] on page 142 for detailed description of access rules.
Offset ^103h
Bits
Description
7:0 EC2OS_DATA_BYTE_3
This is byte 3 of the 32-bit EC2OS DATA BYTES[3:0].
Type
R/W
Default
0h
Reset
Event
VCC1_R
ESET
10.13.9 EC STATUS REGISTER
This register is aliased to the OS STATUS OS Register on page 136. The OS STATUS OS Register is a read only version
of this register.
Offset ^104h
Bits
7 UD0A
User Defined
Description
Type
R/W
Default
0b
Reset
Event
VCC1_R
ESET
6 SMI_EVT
R/W
See SMI_EVT bit in OS STATUS OS Register on page 136 for bit
description.
5 SCI_EVT
R/W
See SMI_EVT bit in OS STATUS OS Register on page 136 for bit
description.
4 BURST
R/W
See BURST bit in OS STATUS OS Register on page 136 for bit
description.
0b
VCC1_R
ESET
0b
VCC1_R
ESET
0b
VCC1_R
ESET
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DS00001719D-page 143