MEC1322 Datasheet, PDF (223/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
17.5.1 POWER DOMAINS
TABLE 17-1:
POWER SOURCES
Name
VCC1
17.5.2 CLOCK INPUTS
Description
The timer control logic and registers are all implemented on this single
power domain.
TABLE 17-2: CLOCK INPUTS
Name
48 MHz Ring Oscillator
17.5.3 RESETS
Description
This is the clock source to the timer logic. The Pre-scaler may be used
to adjust the minimum resolution per bit of the counter.
TABLE 17-3: RESET SIGNALS
Name
VCC1_RESET
Soft Reset
Timer_Reset
Description
This reset signal, which is an input to this block, resets all the logic and
registers to their initial default state.
This reset signal, which is created by this block, resets all the logic and
registers to their initial default state. This reset is generated by the block
when the SOFT_RESET bit is set in the Timer Control Register register.
This reset signal, which is created by this block, is asserted when either
the VCC1_RESET or the Soft Reset signal is asserted. The VCC1_RE-
SET and Soft Reset signals are OR’d together to create this signal.
17.6 Interrupts
TABLE 17-4: EC INTERRUPTS
Source
TIMER_16_x
TIMER_32_x
Description
This interrupt event fires when a 16-bit timer x reaches its limit. This
event is sourced by the EVENT_INTERRUPT status bit if enabled.
This interrupt event fires when a 32-bit timer x reaches its limit. This
event is sourced by the tEVENT_INTERRUPT status bit if enabled.
17.7 Low Power Modes
The Basic Timer may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry. This block
is only be permitted to enter low power modes when the block is not active.
The sleep state of this timer is as follows:
• Asleep while the block is not Enabled
• Asleep while the block is not running (start inactive).
• Asleep while the block is halted (even if running).
The block is active while start is active.
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DS00001719D-page 223