MEC1322 Datasheet, PDF (144/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Offset ^104h
Bits
Description
3 CMD
See CMD bit in OS STATUS OS Register on page 136 for bit
description.
2 UD1A
User Defined
Type
R
R/W
1 IBF
R
See IBF bit in OS STATUS OS Register on page 136 for bit descrip-
tion.
0 OBF
R
See OBF bit in OS STATUS OS Register on page 136 for bit descrip-
tion.
Default
0b
Reset
Event
VCC1_R
ESET
0b
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
Note:
The IBF and OBF bits are not de-asserted by hardware when the host is powered off, or the LPC interface
powers down; for example, following system state changes S3->S0, S5->S0, G3-> S0. For further informa-
tion on how these bits are cleared, refer to IBF and OBF bit descriptions in the STATUS OS-Register defi-
nition.
10.13.10 EC BYTE CONTROL REGISTER
This register is aliased to the OS Byte Control Register on page 140. The OS Byte Control Register is a read only version
of this register.
Offset ^105h
Bits
Description
7:1 Reserved
0 FOUR_BYTE_ACCESS
See FOUR_BYTE_ACCESS bit in OS Byte Control Register on
page 140 for bit description.
Type
R
R/W
Default
-
0b
Reset
Event
-
VCC1_R
ESET
DS00001719D-page 144
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