MEC1322 Datasheet, PDF (207/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 15-12: BIT DEFINITIONS FOR GIRQ9 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name Wake
Source Description
[30:24] GPIO[136:130]
GPIO_Event
Y Bits[24:30] are controlled by the GPIO_Events gener-
ated by GPIO130 through GPIO136, respectively.
31
n/a
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the
GPIO signal function.
n/a
N See Table 15-7, "GIRQx Source Register", Table 15-8,
"GIRQx Enable Set Register", Table 15-10, "GIRQx
Enable Clear Register", and Table 15-9, "GIRQx
Result Register" for a definition of this bit for the
Source, Enable, and Result registers.
15.9.3 GIRQ10
TABLE 15-13: BIT DEFINITIONS FOR GIRQ10 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
[7:0] GPIO[047:040]
GPIO_Event
Y Bits[0:7] are controlled by the GPIO_Events generated by
GPIO040 through GPIO047, respectively.
[15:8] GPIO[057:050]
GPIO_Event
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
Y Bits[8:15] are controlled by the GPIO_Events generated
by GPIO050 through GPIO057, respectively.
[23:16] GPIO[067:060]
GPIO_Event
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
Y Bits[16:23] are controlled by the GPIO_Events generated
by GPIO060 through GPIO067, respectively.
[30:24]
31
Reserved
n/a
Reserved
n/a
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
N Reserved
N See Table 15-7, "GIRQx Source Register", Table 15-8,
"GIRQx Enable Set Register", Table 15-10, "GIRQx
Enable Clear Register", and Table 15-9, "GIRQx Result
Register" for a definition of this bit for the Source, Enable,
and Result registers.
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DS00001719D-page 207